TLK2711-SP Datasheet, PDF (10/21 Pages) Texas Instruments – 1.6-Gbps to 2.5-Gbps Class V Transceiver

TLK2711-SP
SGLS307D – JULY 2006 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com
Power-Down Mode
The TLK2711 goes into power-down mode when the ENABLE pin is pulled low. In the power-down mode, the
serial transmit pins (TXN), the receive data bus pins (RXD0–RXD15), and RKLSB goes into a high-impedance
state. In the power-down condition, the signal detection circuit draws less than 15 mW. When the TLK2711 is in
the power-down mode, the clock signal on the TXCLK terminal must be provided if LOS functionality is needed.
Loss of Signal (LOS) Detection
The TLK2711 has a LOS detection circuit for conditions where the incoming signal no longer has a sufficient
voltage level to keep the clock recovery circuit in lock. The signal detection circuit is intended to be an indication
of gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of
signal coding health. The TLK2711 reports this condition by asserting RKLSB, RKMSB, and RXD0–RXD15
terminals to a high state. As long as the differential signal is above 200 mV in differential magnitude, the LOS
circuit does not signal an error condition.
PRBS Verification
The TLK2711 also has a built-in BERT function in the receiver side that is enabled by the PRBSEN. It can check
for errors and report the errors by forcing the RKLSB terminal low.
Reference Clock Input
The reference clock (TXCLK) is an external input clock that synchronizes the transmitter interface. The reference
clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. The internal
serialization bit clock is frequency locked to the reference clock and used to clock out the serial transmit data on
both its rising and falling edges, providing a serial data rate that is 20 times the reference clock.
Operating Frequency Range
The TLK2711 operates at a serial data rate from 1.6 Gbps to 2.5 Gbps. To achieve these serial rates, TXCLK
must be within 80 MHz to 125 MHz. The TXCLK must be within ±100 PPM of the desired parallel data rate clock.
Testability
The TLK2711 has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed
testing of the transmit/receive portions of the circuitry. The enable terminal allows for all circuitry to be disabled
so that a quiescent current test can be performed. The PRBS function allows for built-in self-test (BIST).
Loopback Testing
The transceiver can provide a self-test function by enabling (LOOPEN) the internal loopback path. Enabling this
terminal causes serial-transmitted data to be routed internally to the receiver. The parallel data output can be
compared to the parallel input data for functional verification. The external differential output is held in a
high-impedance state during the loopback testing.
Built-In Self-Test (BIST)
The TLK2711 has a BIST function. By combining PRBS with loopback, an effective self-test of all the circuitry
running at full speed can be realized. The successful completion of the BIST is reported on the RKLSB terminal.
Power-On Reset
Upon application of minimum valid power, the TLK2711 generates a power-on reset. During the power-on reset
the RXD0–RXD15, RKLSB, and RKMSB signal terminals go to a high-impedance state. The RXCLK is held low.
The length of the power-on reset cycle is dependent upon the TXCLK frequency, but is less than 1 ms.
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