TLK2711-SP Datasheet, PDF (14/21 Pages) Texas Instruments – 1.6-Gbps to 2.5-Gbps Class V Transceiver

TLK2711-SP
SGLS307D – JULY 2006 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com
TRANSMITTER/RECEIVER CHARACTERISTICS
V_OD(p)
V_{OD(pp_p)}
V_OD(d)
V_{OD(pp_d)}
V_(cmt)
V_ID
V_(cmr)
I_lkg
C_I
t_t, t_f
t_{d(Tx latency)}
t_{d(Rx latency)}
PARAMETER
Preemphasis VOD, direct,
V_OD(p) = |VTXP – VTXN|
Differential,
peak-to-peak output voltage
with preemphasis
Deemphais output voltage,
|VTXP – VTXN|
Differential, peak-to-peak output voltage with
deemphasis
Transmit common mode voltage range,
(VTXP + VTXN)/2
Receiver input voltage differential,
|VRXP – VRXN|
Receiver common mode voltage range,
(VRXP + VRXN)/2
Receiver input leakage current
Receiver input capacitance
Serial data total jitter (peak to peak)
Differential output signal rise, fall time
(20% to 80%)
Jitter tolerance eye closure
Tx latency
Rx latency
TEST CONDITIONS
Rt = 50 Ω, PREM = high, dc-coupled,
See Figure 9
Rt = 50 Ω, PREM = low, dc coupled,
See Figure 9
Rt = 50 Ω, PREM = high, dc coupled,
See Figure 9
Rt = 50 Ω, PREM = low, dc coupled,
See Figure 9
Rt = 50 Ω, dc coupled, See Figure 9
Rt = 50 Ω, dc coupled, See Figure 9
Rt = 50 Ω, See Figure 9
(1)
(1)
Differential output jitter at 2.5 Gbps,
Random + deterministic, PRBS pattern
Differential output jitter at 1.6 Gbps,
Random + deterministic, PRBS pattern
RL = 50 Ω, CL = 5 pF, See Figure 9
Differential input jitter, random + deterministic,
PRBS pattern at zero crossing⁽¹⁾
See Figure 3
See Figure 6
(1) Nonproduction tested parameters
(2) UI is the time interval of one serialized bit.
MIN
655
590
1310
1180
540
1080
1000
220
1000
–10
0.4
34
76
TYP
800
740
1600
1480
650
1300
1250
1250
4
0.28
0.32
150
MAX UNIT
1100
mV
1050
2200
2100
mV_p-p
950 mV
1900 mV_p-p
1450 mV
1600 mV
2250 mV
10 µA
pF
UI ⁽²⁾
ps
UI
38 Bits
107 Bits
V_OD(p)
V_OD(d)
0V
V_{OD(pp_d)} V_{OD(pp_p)}
t_f
t_r
V_OD(d)
Bit
Bit
Time
Time
V_OD(p)
Figure 9. Differential and Common-Mode Output Voltage
14
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