TLK2711-SP Datasheet, PDF (5/21 Pages) Texas Instruments – 1.6-Gbps to 2.5-Gbps Class V Transceiver

TLK2711-SP
www.ti.com .............................................................................................................................................................. SGLS307D – JULY 2006 – REVISED JULY 2009
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
NAME
PIN NO.
DESCRIPTION
TKLSB
K-code generator (LSB). When TKLSB is high, an 8-bit/10-bit K code is transmitted as controlled
23
I⁽³⁾ by data bits TXD0–TXD7. When TKLSB is low, an 8-bit/10-bit D code is transmitted as controlled
by data bits TXD0–TXD7.
TKMSB
K-code generator (MSB). When TKMSB is high, an 8-bit/10-bit K code is transmitted as controlled
21
I⁽³⁾ by data bits TXD8–TXD15. When TKMSB is low, an 8-bit/10-bit D code is transmitted as controlled
by data bits TXD8–TXD15.
TXCLK
GTX_CLK
Reference clock. TXCLK is a continuous external input clock that synchronizes the transmitter
8
I
interface signals TKMSB, TKLSB, and TXD0–TXD15. The frequency range of TXCLK is 80 MHz to
135 MHz. The transmitter uses the rising edge of this clock to register the 16-bit input data
TXD0–TXD15 for serialization.
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TXD8
TXD9
TXD10
TXD11
TXD12
TXD13
TXD14
TXD15
66
67
68
2
3
4
6
7
10
11
Transmit data bus. These inputs carry the 16-bit parallel data output from a protocol device to the
I transceiver for encoding, serialization, and transmission. This 16-bit parallel data is clocked into
the transceiver on the rising edge of TXCLK as shown in Figure 2.
12
14
15
16
18
20
VDD
1, 9, 24, 40,
50
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
VDDA
59, 61
Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver, and
transmitter.
(3) Internal 10-kΩ pullup
DETAILED DESCRIPTION
Transmit Interface
The transmitter interface registers valid incoming 16-bit-wide data (TXD0–TXD15) on the rising edge of the
TXCLK. The data is then 8-bit/10-bit encoded, serialized, and transmitted sequentially over the differential
high-speed I/O channel. The clock multiplier multiplies the reference clock (TXCLK) by a factor of 10 times,
creating a bit clock. This internal bit clock is fed to the parallel-to-serial shift register, which transmits data on
both the rising and falling edges of the bit clock, providing a serial data rate that is 20 times the reference clock.
Data is transmitted least significant bit (LSB) (TXD0) first.
Transmit Data Bus
The transmit data bus interface accepts 16-bit single-ended TTL parallel data at the TXD0–TXD15 terminals.
Data and K-code control is valid on the rising edge of the TXCLK. The TXCLK is used as the word clock. The
data, K-code, and clock signals must be properly aligned as shown in Figure 2. Detailed timing information can
be found in the electrical characteristics table.
Copyright © 2006–2009, Texas Instruments Incorporated
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