TLK2711-SP Datasheet, PDF (7/21 Pages) Texas Instruments – 1.6-Gbps to 2.5-Gbps Class V Transceiver

TLK2711-SP
www.ti.com .............................................................................................................................................................. SGLS307D – JULY 2006 – REVISED JULY 2009
TKLSB
0
0
1
1
TKMSB
0
1
0
1
Table 1. Transmit Data Controls
16 BIT PARALLEL INPUT
Valid data on TXD0–TXD7,
Valid data TXD8–TXD15
Valid data on TXD0–TXD7,
K code on TXD8–TXD15
K code on TXD0–TXD7,
Valid data on TXD8–TXD15
K code on TXD0–TXD7,
K code on TXD8–TXD15
Pseudo-Random Bit Stream (PRBS) Generator
The TLK2711 has a built-in 2⁷–1 PRBS function. When the PRBSEN terminal is forced high, the PRBS test is
enabled. A PRBS is generated and fed into the 10-bit parallel-to-serial converter input register. Data from the
normal input source is ignored during the PRBS mode. The PRBS pattern is then fed through the transmit
circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester
(BERT), the receiver of another TLK2711, or looped back to the receive input. Since the PRBS is not really
random but a predetermined sequence of ones and zeroes, the data can be captured and checked for errors by
a BERT.
Parallel to Serial
The parallel-to-serial shift register takes in the 20-bit-wide data word multiplexed from the two parallel 8-bit/10-bit
encoders and converts it to a serial stream. The shift register is clocked on both the rising and falling edge of the
internally generated bit clock, which is 10 times the TXCLK input frequency. The LSB (TXD0) is transmitted first.
High-Speed Data Output
The high-speed data output driver consists of a voltage mode logic (VML) differential pair optimized for a 50-Ω
impedance environment. The magnitude of the differential pair signal swing is compatible with pseudo emitter
coupled logic (PECL) levels when ac coupled. The line can be directly coupled or ac coupled. See Figure 13 and
Figure 14 for termination details. The outputs also provide preemphasis to compensate for ac loss when driving a
cable or PCB backplane trace over a long distance (see Figure 4). The level of preemphasis is controlled by PRE
(see Table 2 ).
V_OD(p)
V_OD(d)
0V
Bit
Time
Bit
Time
V_OD(p)
V_OD(d)
Figure 4. Output Voltage Under Preemphasis
(VTXP–VTXN)
Table 2. Programmable Preemphasis
PRE
0
1
PREEMPHASIS LEVEL (%)
V_OD(P), V_OD(D) ⁽¹⁾
5%
20%
(1) V_OD(p): Voltage swing when there is a transition in the data
stream.
V_OD(d): Voltage swing when there is no transition in the data
stream.
Receive Interface
The receiver interface of the TLK2711 accepts 8-bit/10-bit encoded differential serial data. The interpolator and
clock recovery circuit locks to the data stream and extracts the bit-rate clock. This recovered clock is used to
retime the input data stream. The serial data is then aligned to two separate 10-bit word boundaries, 8-bit/10-bit
decoded, and output on a 16-bit-wide parallel bus synchronized to the extracted receive clock. The data is
received LSB (RXD0) first.
Receive Data Bus
The receive bus interface drives 16-bit-wide single-ended TTL parallel data at the RXD0–RXD15 terminals. Data
is valid on the rising edge of the RXCLK. The RXCLK is used as the recovered word clock. The data, RKLSB,
RKMSB, and clock signals are aligned as shown in Figure 5. Detailed timing information can be found in the
switching characteristics table.
Copyright © 2006–2009, Texas Instruments Incorporated
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