TLK2711-SP Datasheet, PDF (4/21 Pages) Texas Instruments – 1.6-Gbps to 2.5-Gbps Class V Transceiver

TLK2711-SP
SGLS307D – JULY 2006 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com
TERMINAL
NAME
PIN NO.
DOUTTXN
63
DOUTTXP
64
ENABLE
GND
25
5, 13, 17,
19, 29, 34,
35, 45, 51,
55, 58, 62,
65
LCKREFN
26
LOOPEN
22
PRE
60
PRBSEN
27
RKLSB
30
RKMSB
31
RXCLK
RX_CLK
43
RXD0
54
RXD1
53
RXD2
52
RXD3
49
RXD4
48
RXD5
47
RXD6
46
RXD7
44
RXD8
42
RXD9
41
RXD10
39
RXD11
38
RXD12
37
RXD13
36
RXD14
33
RXD15
32
DINRXN
56
DINRXP
57
TESTEN
28
(1) Internal 10-kΩ pullup
(2) Internal 10-kΩ pulldown
TERMINAL FUNCTIONS
I/O
DESCRIPTION
Serial transmit outputs. TXP and TXN are differential serial outputs that interface to copper or an
O
optical I/F module. These terminals transmit NRZ data at a rate of 20 times the TXCLK value. TXP
and TXN are put in a high-impedance state when LOOPEN is high and are active when LOOPEN
is low. During power-on reset, these terminals are high impedance.
Device enable. When this terminal is held low, the device is placed in power-down mode. Only the
I⁽¹⁾ signal detect circuit on the serial receive pair is active. When asserted high while the device is in
power-down mode, the transceiver goes into power-on reset before beginning normal operation.
Analog and digital logic ground. Provides a ground for the logic circuits, digital I/O buffers, and the
high-speed analog circuits.
Lock to reference. When LCKREFN is low, the receiver clock is frequency locked to TXCLK. This
places the device in a transmit-only mode since the receiver is not tracking the data. When
I⁽¹⁾ LCKREFN is asserted low, the receive data bus terminals (RXD0–RXD15, RXCLK, RKLSB, and
RKMSB) are in a high-impedance state.
When LCKREFN is deasserted high, the receiver is locked to the received data stream.
Loop enable. When LOOPEN is active high, the internal loopback path is activated. The
transmitted serial data is directly routed internally to the inputs of the receiver. This provides a
I⁽²⁾ self-test capability in conjunction with the protocol device. The TXP and TXN outputs are held in a
high-impedance state during the loopback test. LOOPEN is held low during standard operational
state, with external serial outputs and inputs active.
Preemphasis control. Selects the amount of preemphasis to be added to the high-speed serial
I⁽²⁾ output drivers. Left low or unconnected, 5% preemphasis is added. Pulled high, 20% preemphasis
is added.
I ⁽²⁾
PRBS test enable. When asserted high, results of pseudo-random bit stream (PRBS) tests can be
monitored on the RKLSB terminal. A high on RKLSB indicates that valid PRBS is being received.
K-code indicator/PRBS test results. When RKLSB is asserted high, an 8-bit/10-bit K code was
O
received and is indicated by data bits RXD0–RXD7. When RKLSB is asserted low, an 8-bit/10-bit
D code is received and is presented on data bits RXD0–RXD7. When PRBSEN is asserted high,
this pin is used to indicate status of the PRBS test results (high = pass).
K-code indicator. When RKMSB is asserted high an 8-bit/10-bit K code was received and is
O
indicated by data bits RXD8–RXD15. When RKMSB is asserted low an 8-bit/10-bit D code was
received and is presented on data bits RXD8–RXD15. If the differential signal on RXN and RXP
drops below 200 mV, RXD0–RXD15, RKLSB, and RKMSB are all asserted high.
O
Recovered clock. Output clock that is synchronized to RXD0–RXD9, RKLSB, and RKMSB. RXCLK
is the recovered serial data rate clock divided by 20. RXCLK is held low during power-on reset.
Receive data bus. These outputs carry 16-bit parallel data output from the transceiver to the
O protocol device, synchronized to RXCLK. The data is valid on the rising edge of RXCLK as shown
in Figure 5. These terminals are in high-impedance state during power-on reset.
I
Serial receive inputs. RXP and RXN together are the differential serial input interface from a
copper or an optical I/F module.
I⁽²⁾ Test mode enable. This terminal should be left unconnected or tied low.
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