DDC101 Datasheet, PDF (8/29 Pages) Burr-Brown (TI) – 20-BIT ANALOG-TO-DIGITAL CONVERTER

Continuous Integration Timing
SYSTEM
CLOCK
FDS In
Internal
Oversampling
Interval
Internal
Reset
DATA VALID
Out
T_INT'
T_INT
t₁
FDS In should be coincident with negative clock.
t₂
FDS initiates oversampling period.
M Clock Periods
End of oversample period
initiates reset for next integration.
M Clock Periods
Next integration begins when 1 clock
period wide Internal Reset ends.
Non-Continuous Integration Timing
SYSTEM
CLOCK
FDS In
Internal
Oversampling
Interval
Internal
Reset
DATA VALID Out
FDS In should be coincident with negative clock.
t₃
FDS initiates oversampling period.
End of FDS In
initiates end of Internal Reset.
End of oversample _t4
period initiates
reset.
When Internal Reset period ends,
next integration begins.
FIGURE 4. Conversion Timing Diagrams.
RESET SETUP In
DATA CLOCK
(4MHz, max for setup)
SETUP In
t₅
t₆ ^Read
t₇
Read
ACQ_MSB ACQ_LSB
FIGURE 5. Input/Output Timing Diagram—SETUP Timing Diagram.
Read Read
Input Output
Range Format
SYSTEM
CLOCK
t₈
DATA VALID
Out
DATA TRANSMIT
In
DATA CLOCK
(8MHz, max for data)
t₉
t₁₇
DATA TRANSMIT In resets DATA VALID Out.
t₁₀ Data can be read on rising or falling edge of Data Clock
DATA OUTPUT
t₁₁
t₁₂
Output Disabled
DDC(1)
Bit 1, MSB
Output Enabled
FIGURE 6. DATA TRANSMIT Timing Diagram.
®
DDC101
8
DDC(n)
Bit 21, LSB
DDC
(n+1)
Bit 1
t₁₃
Output Disabled
Last DDC
Bit 21