DDC101 Datasheet, PDF (18/29 Pages) Burr-Brown (TI) – 20-BIT ANALOG-TO-DIGITAL CONVERTER

I_FS
1nA
10nA
100nA
1µA
5µA
7.8µA
T_INT
500ms
50ms
5ms
500µs
100µs
64µs
TABLE III. Input Current vs Integration Time Examples
for Maximum Charge. Unipolar input range
maximum charge = 500pC.
Conversion Cycle
Integration 1
Integration 2
Time
±I_FS
1nA
10nA
100nA
1µA
2.5µA
7.8µA
T_INT
250ms
25ms
2.5ms
250µs
100µs
32µs
CDAC
Charge
One data output per
conversion cycle with
two integrations/conversion
TABLE IV. Input Current vs Integration Time Examples
for Maximum Charge. Bipolar input range
maximum charge = ±250pC.
MULTIPLE INTEGRATIONS
PER CONVERSION CYCLE
If more than 500pC, unipolar (or ±250pC, bipolar) of charge
must be integrated in one conversion cycle, the DDC101 can
be user programmed for multiple integrations per conversion
cycle. This feature can be used to provide for longer conver-
sion periods for a specific input current other than shown in
the previous table. The integration cycles forming a conver-
sion cycle may be continuous or non-continuous. The num-
ber of integrations per conversion cycle, L, can be 1, 2, 4, 8,
16, 32, 64, 128, or 256. The multiple integrations are
automatically averaged in the DDC101 so that one conver-
sion result is output per total conversion cycle. Note that
each integration requires individual control by the FDS
signal. For example, if L = 4, then four FDS signals per
conversion are required.
FINAL DATA POINT CONFIGURATION LIMITS
In each conversion cycle, the maximum number of final data
points which can be collected is 256. This means that at the
extremes, the DDC101 can be setup to perform one integra-
tion cycle with 256 oversamples, or the DDC101 can be
setup to perform 256 integration cycles with one sample per
integration cycle. The total number of integrations, L, mul-
tiplied by the number of samples per final data point, must
be 256 or less. As an example, if 16 integration cycles, L, are
used, the number of samples per final data point must be 16
or less.
NOTE: When CDS is used, the initial data points impose no
additional conversion sampling limitations.
FIGURE 15. Conversion Cycle with Two Integrations.
INTEGRATIONS
PER CONVERSION
L=1
L=2
L=4
L=8
L = 16
L = 32
L = 64
L = 128
L = 256
I
FS
10nA
10nA
10nA
10nA
10nA
10nA
10nA
10nA
10nA
CONVERSION
TIME
50ms
100ms
200ms
400ms
800ms
1.6s
3.2s
6.4s
12.8s
MAX CHARGE/
CONVERSION
500pC
1000pC
2000pC
4000pC
8000pC
16000pC
32000pC
64000pC
128000pC
TABLE V. Integrations/Conversion vs Conversion Time.
Example for multiple integrations with unipolar
input range.
individual component has a sinc (sinx/x) frequency response
function.
1. Basic Integration
This is the characteristic sin(x)/x response of the basic
integration function. This response is controlled by the
measurement time of the DDC101, T_MEAS; see Figure 16.
2. Oversampling
This is the low pass filter characteristic of the digital
filter’s oversampling. This response reduces the broad-
band noise in the input signal of the DDC101. Broadband
noise decreases as the number of oversamples increases.
This response is controlled by the number of oversamples,
M; see Figure 17.
3. Multiple Integrations
This is the low pass filter characteristic that results when
the digital filter is used to average multiple integrations.
This will determine the primary response of the DDC101
if two or more integrations are internally averaged. This
response is controlled by the total conversion time of the
DDC101; see Figure 18.
FREQUENCY RESPONSE
Input frequencies are multiplied by the DDC101 frequency
The DDC101 charge digitizing A/D Converter is a sampled
system whose frequency response has three separate compo-
nents. These components are multiplied together to make the
total frequency characteristic of the DDC101. The three
response. The Nyquist frequency is f_CONV/2, where f_CONV is
the DDC101 conversion rate. The highest frequency that can
be reconstructed from the output data is f_CONV/2. Input
frequencies above Nyquist are multiplied by the DDC101
frequency response components are shown below. Each
frequency response and are then aliased into DC to f_CONV/2.
®
DDC101
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