DDC101 Datasheet, PDF (23/29 Pages) Burr-Brown (TI) – 20-BIT ANALOG-TO-DIGITAL CONVERTER

Oversampling Control
Samples/Integration—M - 4 bits
CODE
0000
0001
0010
0011
0100
0101
0110
0111
1XXX
SAMPLES PER INTEGRATION
1
2
4
8
16
32
64
128
256
Multiple Integration Control
Integrations/Conversion—L - 4 bits
CODE
0000
0001
0010
0011
0100
0101
0110
0111
1XXX
INTEGRATIONS PER CONVERSION
1
2
4
8
16
32
64
128
256
Input Range - 1 bit
CODE
0
1
INPUT RANGE
Unipolar
Bipolar
Output Format - 1 bit
CODE
1
0
OUTPUT FORMAT
Binary Two's Complement
Straight Binary
Pin 1
Guard
Pattern
DDC101
V_S–
Analog Common
Analog Input
Analog Common
FIGURE 22. PC Board Layout Showing “Guard” Traces
Surrounding Analog Input Pin and Traces.
Power Supplies
The ±5VDC supplies of the DDC101 should be bypassed
with 10µF solid tantalum capacitors and 0.1µF ceramic
capacitors. The supplies should each have a 10µF solid
tantalum capacitor at a central point on the PC board. Each
of the DDC101 power supply lines (V_S+, V_S–, V_DD+) should
have a separate 0.1µF ceramic capacitor placed as close to
the DDC101 package as possible.
The digital power supply voltage, V_DD+ must be equal to or
less than the analog power supply voltage, V +. The analog
S
power supply, V_S+, is connected to pins 5 and 6, these pins
should be hardwired together on the printed circuit board at
the pins for best performance.
V_DD+ should be as quiet as possible with minimal noise
coupling. It is particularly important to eliminate noise from
V_DD+ that is non-synchronous with DDC101 operation.
Figure 23 illustrates two acceptable ways to supply V_DD+
power to the DDC101. The first case shows two separate
+5VDC supplies for V_DD+ and V_S+. The second case shows
the V_DD+ power supply derived from the V_S+ supply as used
on the DDC101 Evaluation Fixture Device Under Test
(DUT) board.
V_S+
SECTION 7
APPLICATIONS INFORMATION
BASIC PRINTED CIRCUIT BOARD LAYOUT
10µF
V_DD+
0.1µF
5
6
DDC101
As with any precision circuit, careful printed circuit layout
will ensure best performance. Make short, direct intercon-
nections and avoid stray wiring capacitance—particularly at
the analog input pin. Digital signals should be kept as far
from the analog input signals as possible on the PC board.
Leakage currents between PC board traces can exceed the
input bias current of the DDC101 if care is not taken. A
circuit board “guard” pattern for the analog input pin and for
the PC board trace that connects to the analog input pin is
recommended. The guard pattern reduces leakage effects by
surrounding the analog input pin and trace with a low
impedance analog ground. Leakage currents from other
portions of the circuit will flow harmlessly to the low
impedance analog ground rather than into the analog input
of the DDC101. Analog ground pins are placed on either
side of the analog input pin in the DDC101 package to allow
convenient layout of guard patterns. Figure 22 illustrates the
use of guard patterns to protect the analog input.
10µF
12
0.1µF
Separate +5VDC Supplies
V_S+
10µF
10Ω
0.1µF
5
6
DDC101
12
0.1µF
One +5VDC Supply
FIGURE 23. Positive Supply Connection Options.
®
23
DDC101