DDC101 Datasheet, PDF (14/29 Pages) Burr-Brown (TI) – 20-BIT ANALOG-TO-DIGITAL CONVERTER

constraint is, the voltage that appears at the DDC101 input,
must not exceed 2.5V. If this voltage is exceeded, charge
may be lost and the integration result may be invalid. The
input voltage can be calculated:
i(t)
=
C_S
dv
dt
or
V
=
1
C_S
∫
i(t)dt
therefore,
V=i ^t .
C_S
As an example, with a user supplied input capacitance of
100pF, a current pulse of 100µA for 2µs could be stored
without exceeding 2.5V applied to the input:
V = (100µA) • ^2µs = 2V.
100 pF
The current pulse must occur completely during part of one
DDC101 integration time, and the DDC101 must still have
time to discharge the input capacitance to ground at a
maximum rate of 7.8µA before the DDC101 is triggered
(through the FDS input) to end the integration. In addition,
the total charge integrated must be 500pC or less for the
unipolar range. A current pulse of 100µA for 2µs creates
200pC of charge.
VOLTAGE INPUT SPECIFICATIONS
The DDC101 is a charge digitizing device. With a user
provided input resistor, the DDC101 can digitize voltage
inputs. All of the general charge/current input specifications
apply to the voltage input situation. The specification table
shows the typical noise of the DDC101 including the effects
of a 20MΩ input resistor, R_IN.
The input of the DDC101 is a virtual ground. A voltage input
causes a current, i, to flow into the input through R_IN as
shown in Figure 9b. The maximum input current is deter-
mined by the integration time selected. Table II shows the
Current Input Configuration
i
Analog Input, pin 3
DDC101
Analog Common
Data Out
maximum input voltage based upon several selections of
input current and input resistor for unipolar input range. The
accuracy of the input resistor will add directly to the DC
Gain Error of the DDC101; the drift of the input resistor will
add directly to the Gain Drift of the DDC101.
Note that the DDC101 output noise decreases as R_IN in-
creases. This is because the DDC101 noise gain decreases
and the input resistance current noise decreases as R_IN
increases. This effect is shown in the “Noise vs Resistor
Value” typical performance curve.
INTEGRATION TIME
Full Scale Input Current
Full Scale Voltage
50mV
500mV
5V
50V
INPUT RESISTOR, R_IN
1ms
500µs
0.5µA
1µA
100µs
5µA
100kΩ
1MΩ
10MΩ
100MΩ
50kΩ
500kΩ
5MΩ
50MΩ
10kΩ
100kΩ
1MΩ
10MΩ
TABLE II. Example of Input Resistor Values Unipolar Input
Range.
UNIPOLAR LINEARITY ERRORS
Due to innovative design techniques, the absolute level of
linearity error of the DDC101 improves as the input signal
level decreases when used in the unipolar input mode.
Therefore, in unipolar input mode, the integral linearity of
the DDC101 is specified as a small base error plus a
percentage of reading error or as a percentage of full scale
range. A best-fit straight line method is used to determine
integral linearity. Two different best-fit straight lines are
used for the two unipolar integral linearity specifications.
For bipolar input mode, linearity is specified only as a
percentage of full scale range.
To illustrate the improvement in unipolar mode linearity
error, Figure 10 shows the maximum unipolar integral lin-
earity error (ILE) of the DDC101 as a function of the input
signal level. The maximum integral linearity error is
±0.0244% of reading ±2.5ppm of FSR (ILE max for unipo-
lar input of –1.95 to 0 pc is ±0.0244% of reading ±3.0ppm
of FSR). Thus, the maximum ILE for an input level of 1%
of FSR is 0.0005%FSR.
0.1
0.01
Voltage Input Configuration
Input
Resistor _i
V ^RIN
Analog Input, pin 3
DDC101
Data Out
Analog Common
FIGURE 9b. DDC101 Input Configurations.
®
DDC101
0.001
0.0001
0.001
0.01
0.1
1
10
100
Unipolar Input Level (% of FSR)
FIGURE 10. Maximum Unipolar Integral Linearity Error
Relative to Full-Scale, Converted From % of
Reading Specification.
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