DDC101 Datasheet, PDF (15/29 Pages) Burr-Brown (TI) – 20-BIT ANALOG-TO-DIGITAL CONVERTER

NOISE
The noise of the DDC101 improves as the input signal level
decreases, thus very low level signals can be resolved. Noise
is shown in the specification table for low level inputs. For
unipolar input range, the DDC101 noise at low level inputs
is dominated by comparator noise gained to the output; at
full scale inputs, the noise is dominated by D/A converter
noise. The noise at low low level inputs is a function of input
capacitance; the noise at full scale is relatively independent
of input capacitance. For bipolar input operation, the noise
is dominated by D/A converter noise and is higher than the
full scale unipolar noise.
BIPOLAR INPUT ACCURACY
Linearity—As a bipolar input device, the linearity of the
DDC101 is specified as a percentage of full scale range that
does not improve with lower input signal levels. Perfor-
mance is generally limited by the linearity of the unit when
operated in the bipolar input mode.
Noise—In general, noise is not as important as linearity
when determining total error. The output noise of the DDC101
in the bipolar mode peaks at midscale (zero input signal
level). Output noise is lower for inputs above and below
zero.
RESET CHARGE ERROR
The reset charge error (typically less than 250fC) is an offset
error that could result from offset voltage, charge injection
and kT/C errors. The DDC101 eliminates the effects of reset
charge errors with correlated double sampling.
DC BIAS VOLTAGE
The DDC101 generates a small bias voltage (typically 500µV)
at the input. This voltage is impressed on any sensor that is
connected to the input. The DC bias voltage is the actual
virtual ground voltage of the DDC101. The DDC101 input
comparator circuitry includes an autozero circuit which
eliminates this offset internally so that it does not produce an
output error.
GAIN SENSITIVITY TO V_REF
The DDC101 gain is dependent upon the external reference
voltage, V_REF. A change in the value of V_REF will be seen as
a directly proportional change in the gain of the DDC101.
FREQUENCY RESPONSE
The DDC101 is a sampling system whose transfer function
has three separate frequency components. These compo-
nents are multiplied together to make the total frequency
characteristic of the DDC101. The three components are:
1. Basic Integration
This is the characteristic sin(x)/x response of the basic
integration function. This response is controlled by the
integration time of the DDC101.
2. Oversampling
This is the low pass filter characteristic of the digital
filter’s oversampling. This response reduces the broad-
band noise in the input signal and the DDC101. Broad-
band noise decreases as the number of oversamples
increases.
3. Multiple Integrations
This is the low pass filter characteristic that results when
the digital filter is used to average multiple integrations.
This will determine the primary response of the DDC101
if two or more integrations are internally averaged.
See Section 6 for more details.
SECTION 6
DETAILED THEORY
OF OPERATION
INTEGRATION CYCLE
An integration cycle, as illustrated in Figure 11, includes the
Acquisition Time, Initial Data Point Sampling, Tracking
Interval, and Final Data Point Sampling. The Acquisition
Time is K clock periods. The first clock cycle of the
Acquisition Time is used to reset the integrating capacitor,
C_INT, to zero from the previous integration. The balance of
the Acquisition Time insures that the DDC101 system is
accurately tracking the input signal prior to initial data point
acquisition. Close-ups of the Reset and Acquisition time are
shown in Figures 12 and 13.
The Initial Data Point is then sampled M times. The Integra-
tion cycle time consists primarily of the Tracking Interval
during which time the DDC101 “tracks” the integration of
the input signal. The Tracking Interval is followed by the
measurement of the Final Data Point with the same user
selected number of samples, M. M and K are user selectable.
The entire integration cycle consists of N clock periods as
controlled by the user.
The DDC101 operates in continuous and non-continuous
integration modes. In the continuous mode, one integration
follows another with no delay from the end of one integra-
tion to the beginning of the next conversion. In the non-
continuous mode, each new integration is started separately
under user control.
The Final Data point Start (FDS) input is the primary user
control of the integration cycle. The FDS input controls the
end of one integration cycle and the start of the next
integration cycle in both the continuous and non-continuous
integration modes. Measurement of the M final data point
samples begins when the FDS input is activated.
CONTINUOUS INTEGRATION MODE
In the continuous integration mode, the “Final Data Point
Start” command (using the FDS pin) initiates the measure-
ment of the M final data point samples. The next integration
cycle begins immediately after the final data point sampling
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DDC101