DDC101 Datasheet, PDF (17/29 Pages) Burr-Brown (TI) – 20-BIT ANALOG-TO-DIGITAL CONVERTER

Acquisition Time, K
Actual Integration
Ideal Integration
Reset of
Previous Integration
Signal Acquired
FIGURE 13. Close-up of Reset and Acquisition Time for
DDC101.
Integration n
Integration n + 1
Correlated Double Sampling is implemented in the DDC101
by subtracting the Initial Data Point from the Final Data
Point. Thus, the error correction is updated automatically for
each integration. When operating in the unipolar input range,
CDS functions with either output data format—straight
binary or binary two’s complement. When operating in the
bipolar input range, CDS functions with binary two’s comple-
ment output data format only.
The errors that CDS removes are charge injection, kT/C and
DDC101 input voltage offset. These errors are very difficult
to eliminate in equivalent analog circuits. Charge injection
errors result from charge that is transferred through the reset
switch into the integration capacitor. kT/C errors are switch-
ing errors due to the noise of the resistance of the reset
switch. DDC101 voltage offset errors are due to input offset
of the input comparator. Both initial offset and offset drift
with time and temperature are corrected since the correction
is performed each integration cycle.
Final
Oversampled
Data
Initial
Oversampled
Data
Acquisition
Tracking Interval
Reset
Final Data Point Start
FIGURE 14. Close-up of End of One Integration Cycle and
Beginning of Next.
NON-CONTINUOUS INTEGRATION MODE
For the non-continuous integration mode, FDS controls the
start of the M final data point samples and the end of
integration as discussed above. In this mode, however, FDS
is also used to control the start of a new integration cycle
asynchronously with the end of the previous integration.
When FDS transitions to “ON”, the collection of the M final
data point samples begins. At the end of each integration, the
DDC101 automatically resets the integration capacitance. If
FDS remains “ON” past the end of integration, the DDC101
will stay in the integration reset state until FDS transitions to
“OFF”. Holding FDS “ON” past the end of integration will
also reset the DDC101’s tracking logic to zero integration
rate.
In non-continuous integration mode, the initial data point
measurement may be less accurate since the DDC101’s
internal tracking logic is reset at the beginning of the
integration and tracking may not be accurate for the initial
data point measurement. In this situation, Correlated Double
Sampling (CDS) operation may not be advantageous.
INTERNAL ERROR CORRECTION
The DDC101 uses CDS techniques to gain optimum perfor-
mance. CDS removes internal DDC101 errors which occur
for a given integration cycle such as, charge injection, kT/C,
and DDC101 offset errors. Correlated Double Sampling is
user selectable. It is recommended for most continuous
measurement applications.
SINGLE CYCLE INTEGRATION
The DDC101 acquires charge (q) by integrating input cur-
rent (i) for a specific time (T). That is,
T
q = _∫ i dt
O
The DDC101 acquires up to 500pC of full scale charge per
integration cycle in the unipolar input range, and approxi-
mately ±250pC of full scale charge in the bipolar input
range. Therefore, for the DDC101, maximum values can be
calculated.
Unipolar Input Range Bipolar Input Range
500pC = I_FS x T_INT
±250pC = ±I_FS x T_INT
Where I_FS is the full scale input current and T_INT is the
integration time of the DDC101. Examples of I_FS and T_INT
that equal 500pC and ±250pC are shown in the following
tables.
The maximum average input current that the DDC101 can
integrate is 7.8µA. This results in a minimum integration
time of 64µs for unipolar inputs and 32µs for bipolar inputs.
Further flexibility is possible with multiple integration cycles
per conversion as described in the following text.
INPUT RANGE
Unipolar Input Range
For the unipolar input range, the range of charge for each
integration cycle is from positive full scale of +500pC to a
slightly negative charge of –1/256 (approximately –0.4%) of
the positive full scale charge. This is +500pC to –1.95pC.
The negative charge measurement capability allows for low
level PC board parasitic leakages.
Bipolar Input Range
For the bipolar input range, the range of charge for each
integration cycle is from positive full scale of +250pC to
negative full scale of –251.95pC.
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DDC101