AMC7812B_15 Datasheet, PDF (76/92 Pages) Texas Instruments – 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors

AMC7812B
SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013
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HW-DAC-CLR-EN 1 Register (Read or Write, Address = 57h, Default = 0000h)
This register determines which DAC is in a clear state when the DAC-CLR-1 pin goes low.
MSB
BIT
15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT
BIT 3 2
0
H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR
11
10
9
8
7
6
5
4
3
2
1
0
0
LSB
BIT BIT
10
00
Bits[14:3]
H1CLRn
Hardware clear DAC-n enable 1 bit.
0 = Pulling the DAC-CLR-1 pin low does not effect the state of DAC-n
1 = DAC-n is forced into a clear state when the DAC-CLR-1 pin goes low
DAC Configuration Register (Read or Write, Address = 58h, Default = 0000h)
MSB
BIT 15
0
BIT 14
0
BIT 13 BIT 12 BIT 11
0
0
SLDA
11
BIT 10
SLDA
10
BIT 9
SLDA
9
BIT 8
SLDA
8
BIT 7
SLDA
7
BIT 6
SLDA
6
BIT 5
SLDA
5
BIT 4
SLDA
4
BIT 3
SLDA
3
BIT 2
SLDA
2
BIT 1
SLDA
1
LSB
BIT 0
SLDA
0
Bits[11:0]
SLDA-n
DAC synchronous load enable bit.
0 = Asynchronous load is enabled. A write command to the DAC-n-data register immediately updates the DAC-n latch
and the output of DAC-n. The synchronous load DAC signal (ILDAC) does not affect DACn. the default value of SLDA-n
is '0'. The device updates the DAC latch only if the ILDAC bit is set ('1'), thereby eliminating unnecessary glitches. Any
DAC channels that are not accessed are not reloaded. When the DAC latch is updated, the corresponding output
changes to the new level immediately. Note that the SLDA-n bit is ignored in auto mode (DAC-n mode bits do not equal
'00'). In auto mode, the DAC latch is always updated asynchronously.
1 = Synchronous load is enabled. When internal load DAC signal ILDAC occurs, the DAC-n latch is loaded with the value
of the corresponding DACn-data register, and the output of DAC-n is updated immediately. The internal load DAC signal
ILDAC is generated by writing a '1' to the ILDAC bit in the AMC configuration register. In synchronous load, a write
command to the DAC-n-data register updates that register only, and does not change the DAC-n output.
NOTE
The DACs can be forced to a clear state immediately by the external DAC-CLR-n signal,
by alarm events, and by writing to the SW-DAC-CLR register. In these cases, the SLDA-n
bit is ignored.
DAC Gain Register (Read or Write, Address = 59h, Default = 0000h)
The DACn GAIN bits specify the output range of DACn.
MSB
BIT 15 BIT 14 BIT 13 BIT 12
0
0
0
0
BIT 11
DAC11
GAIN
BIT 10
DAC10
GAIN
BIT 9
DAC9
GAIN
BIT 8
DAC8
GAIN
BIT 7
DAC7
GAIN
BIT 6
DAC6
GAIN
BIT 5
DAC5
GAIN
BIT 4
DAC4
GAIN
BIT 3
DAC3
GAIN
BIT 2
DAC2
GAIN
BIT 1
DAC1
GAIN
LSB
BIT 0
DAC0
GAIN
Bits[11:0]
DACnGAIN: DACn gain bits.
1 = Gain is 5 and the output is 0 V to 5 × V_REF
0 = Gain is 2 and the output is 0 V to 2 × V_REF
76
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