AMC7812B_15 Datasheet, PDF (56/92 Pages) Texas Instruments – 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors

AMC7812B
SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013
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Serial Peripheral Interface (SPI)
The AMC7812B can be controlled over a versatile 3-wire serial interface that operates at clock rates of up to 50
MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards. The SPI communication
command consists of a read or write (R/W) bit, seven register address bits, and 16 data bits (as shown in
Table 9), for a total of 24 bits. The timing for this operation is shown in the SPI timing diagrams (Figure 3,
Figure 4, and Figure 5).
SPI Shift Register
The SPI shift register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the control
of the serial clock input, SCLK. The CS falling edge starts the communication cycle. Data are latched into the SPI
shift register on the SCLK falling edge, while CS is low. When CS is high, the SCLK and SDI signals are blocked
out and the SDO line is in a high-impedance state. The contents of the SPI shift register are loaded into the
device internal register on the CS rising edge (with delay). During the transfer, the command is decoded and new
data are transferred into the proper registers.
The serial interface functions with both a continuous and non-continuous serial clock. A continuous SCLK source
can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used and CS must be taken high after the final clock to
latch the data.
AMC7812B Communications Command for SPI
The AMC7812B is entirely controlled by registers. Reading from and writing to these registers is accomplished by
issuing a 24-bit operation word shown in Table 9.
OPERATION
Write
Read frame 1
Read frame 2
Table 9. 24-Bit Word Structure for Read/Write Operation
I/O
SDI
SDO
SDI
SDO
SDI
SDO
BIT 23 (MSB)
0 (R/W)
Data are undefined
1 (R/W)
Data are undefined
1 (R/W)
Data are undefined
BIT22:BIT16
Addr[6:0]
Data are undefined
Addr[6:0]
Data are undefined
Addr[6:0]
Data are undefined
BIT15:BIT0
Data to be written
Undefined or data depending on the
previous frame
Don't care
Undefined or data depending on the
previous frame
Don't care
Data for address specified in frame 1
Bit 23
Bits[22:16]
Bits[15:0]
R/W. Indicates a read from or a write to the addressed register.
0 = The write operation is set and data are written to the specified register
1 = A read operation where bits Addr[6:0] select the register to be read. The remaining bits are don't care. Data read from
the selected register appear on the SDO pin in the next SPI cycle.
Addr6:Addr0. Register address; specifies which register is accessed.
DATA. 16-bit data bits.
In a write operation, these bits are written to bits[15:0] of the register with the address of (Addr[6:0]).
In a read operation, these bits are determined by the previous operation. If the previous operation is a read, these bits are
from bits[15:0] of the internal register specified in previous read operation. If the previous operation is a write, these data
bits are don’t care (undefined). Data read from the current read operation appear on SDO in the next operation cycle.
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