AMC7812B_15 Datasheet, PDF (69/92 Pages) Texas Instruments – 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors

AMC7812B
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SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013
Table 21. Alarm Control Register (continued)
BIT
NAME
DEFAULT
4 EALR-D1-FAIL
0
3 EALR-D2-FAIL
0
2
ALARM-
LATCH-DIS
0
1
—
0
0
—
0
R/W
DESCRIPTION
D1 fail alarm enable bit.
0 = The D1-FAIL alarm is masked. When D1 fails, the ALARM pin does not go low, but the
R/W _{D1-FAIL-ALR bit is set.}
1 = The D1-Fail alarm is enabled. When D1 fails, the D1-FAIL-ALR bit is set ('1'), the
ALARM pin goes low (if enabled).
D2 fail alarm enable bit.
0 = The D2-FAIL alarm is masked. When D2 fails, the ALARM pin does not go low, but the
R/W _{D2-FAIL-ALR bit is set.}
1 = The D2-Fail alarm is enabled. When D2 fails, the D2-FAIL-ALR bit is set ('1'), the
ALARM pin goes low (if enabled).
Alarm latch disable bit.
0 = The status register bits are latched. When an alarm occurs, the corresponding alarm bit
is set ('1'). The alarm bit remains '1' until the error condition subsides and the status
R/W _{register is read. Before reading, the alarm bit is not cleared ('0') even if the alarm condition}
disappears.
1 = The status register bits are not latched. When the alarm condition subsides, the alarm
bits are cleared regardless of whether the status register is read or not.
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
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