AMC7812B_15 Datasheet, PDF (66/92 Pages) Texas Instruments – 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors

AMC7812B
SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013
AMC Configuration Register 0 (Read or Write, Address = 4Ch, Default = 2000h)
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Table 16. AMC Configuration Register 0
BIT
NAME
DEFAULT R/W
DESCRIPTION
15
—
0
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
14
—
0
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
ADC conversion mode bit. This bit selects between the two operating conversion modes
(direct or auto).
13
CMODE
0 = Direct mode. The analog inputs specified in the ADC channel registers are converted
sequentially (see the ADC channel registers) one time. When one set of conversions are
1
R/W _{complete, the ADC is idle and waits for a new trigger.}
1 = Auto mode. The analog inputs specified in the AMC channel registers are converted
sequentially and repeatedly (see the ADC channel registers). When one set of conversions
are complete, the ADC multiplexer returns to the first channel and repeats the process.
Repetitive conversions continue until the CMODE bit is cleared ('0').
12
ICONV
Internal conversion bit.
0
R/W Set this bit to '1' to start the ADC conversion internally. The bit is automatically cleared ('0')
after the ADC conversion starts.
11
ILDAC
Load DAC bit.
Set this bit to '1' to synchronously load the DAC data registers, which are programmed for
synchronous update mode (SLDAC-n = 1). The AMC7812B updates the DAC latch only if
0
R/W the ILDAC bit is set ('1'), thereby eliminating any unnecessary glitches. Any DAC channels
that are not accessed are not reloaded. When the DAC latch is updated, the corresponding
output changes to the new level immediately. This bit is cleared ('0') after the DAC data
register is updated.
10 ADC-REF-INT
0
ADC V_REF select bit.
R/W ^{0 = The internal reference buffer is off and the external reference drives the ADC.}
1 = The internal buffer is on and the internal reference drives the ADC. Note that a
compensation capacitor is required.
9
EN-ALARM
Enable ALARM pin bit.
0
R/W _{0 = The ALARM pin is disabled}
1 = The ALARM pin is enabled
8
—
0
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
ADC Data available flag bit. For direct mode only. Always cleared (set to '0') in Auto mode.
7
DAVF
0 = The ADC conversion is in progress (data are not ready) or the ADC is in auto mode.
1 = The ADC conversions are complete and new data are available.
In direct mode, the DAVF bit sets the DAV pin. DAV goes low when DAVF is '1', and goes
R ^{high when DAVF is '0'.}
In auto mode, DAVF is always cleared to '0'. However, a 1-µs pulse (active low) appears
on the DAV pin when the last input specified in the ADC channel registers is converted.
DAVF is cleared to '0' in one of three ways: by reading the ADC data register, by starting a
new ADC conversion, or by writing '0' to this bit. Reading the status register does not clear
this bit.
6
GALR
Global alarm bit.
0
R
This bit is the OR function of all individual alarm bits of the status register. This bit is set
('1') when any alarm condition occurs, and remains '1' until the status register is read. This
bit is cleared ('0') after reading the status register.
5
—
0
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
4
—
0
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
3
—
0
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
2
—
0
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
1
—
0
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
0
—
0
R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
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