AMC7812B_15 Datasheet, PDF (50/92 Pages) Texas Instruments – 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors

AMC7812B
SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013
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F/S-Mode Protocol
The master initiates the data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high; see Figure 2. All I²C-compatible devices must recognize a
start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read or write direction bit
(R/W) on the SDA line. During all transmissions, the master ensures that data are valid. A valid data condition
requires that the SDA line is stable during the entire high period of the clock pulse (see Figure 2). All devices
recognize the address sent by the master and compare the address to their internal fixed addresses. Only the
slave device with a matching address generates an acknowledge (see Figure 2) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. When this acknowledge is detected, the master recognizes
that a communication link is established with a slave.
The master generates further SCL cycles to either transmit data to the slave (R/W bit is '1') or receive data from
the slave (R/W bit is '0'). In either case, the receiver must acknowledge the data sent by the transmitter.
Therefore, an acknowledge signal can either be generated by the master or by the slave, depending on which
one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue
as long as necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low-to-
high while the SCL line is high (see Figure 2). This action releases the bus and stops the communication link
with the addressed slave. All I²C-compatible devices must recognize the stop condition. When a stop condition is
received, all devices recognize that the bus is released and wait for a start condition followed by a matching
address.
Hs-Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing Hs master code 00001xxx. This
transmission is made in F/S mode at no more than 400 kbps. No device is allowed to acknowledge the Hs
master code, but all devices must recognize the Hs master code and switch their internal setting to support 3.4
Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as for F/S mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends Hs mode and switches all internal settings of the slave
devices to support F/S mode. Note that instead of using a stop condition, repeated start conditions are used to
secure the bus in Hs mode.
Address Pointer
The AMC7812B address pointer register is an 8-bit register. Each register has an address and, when accessed,
the address pointer points to the register address. All AMC7812B registers are 16 bits, consisting of a high byte
(D[15:8]) and a low byte (D[7:0]). The high byte is always accessed first, and the low byte accessed second.
When the register is accessed, the entire register is frozen until the operation on the low byte is complete. During
a write operation, the new content does not take effect until the low byte is written. In read operation, the whole
register value is frozen until the low byte is read.
The address pointer does not change after the current register is accessed. To change the pointer, the master
issues a slave address byte with the R/W bit low, followed by the pointer register byte; no additional data are
required.
Timeout Function
The device resets the serial interface if either SCL or SDA are held low for 32.8 ms (typical) between a START
and STOP condition. If the device is holding the bus low, the device releases the bus and waits for a START
condition. To avoid activating the timeout function, a communication speed of at least 1 kHz for the SCL
operating frequency must be maintained.
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