AM1806_101 Datasheet, PDF (74/243 Pages) Texas Instruments – ARM Microprocessor

AM1806
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
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The maximum voltage slew rate for CVdd supply changes is 1 mV/us.
For additional information on power management solutions from TI for this processor, follow the Power
Management link in the Product Folder on www.ti.com for this processor.
The processor supports multiple clock domains some of which have clock ratio requirements to each
other. PLL0_SYSCLK2:PLL0_SYSCLK4:PLL0_SYSCLK6 are synchronous to each other and the
SYSCLKn dividers must always be configured such that the ratio between these domains is 2:4:1. The
ASYNC and ASYNC3 clock domains are asynchronous to the other clock domains and have no specific
ratio requirement.
The table below summarizes the maximum internal clock frequencies at each of the voltage operating
points.
Table 6-5. Maximum Internal Clock Frequencies at Each Voltage Operating Point
CLOCK SOURCE
PLL0_SYSCLK1
PLL0_SYSCLK2
PLL0_SYSCLK3
PLL0_SYSCLK4
PLL0_SYSCLK5
PLL0_SYSCLK6
PLL0_SYSCLK7
PLL1_SYSCLK1
PLL1_SYSCLK2
PLL1_SYSCLK3
McASP AUXCLK
PLL0_AUXCLK
ASYNC
ASYNC2
ASYNC3
CLOCK DOMAIN
Not used on this processor
SYSCLK2 clock domain peripherals and optional
clock source for ASYNC3 clock domain peripherals
Optional clock for ASYNC1 clock domain
SYSCLK4 domain peripherals
Not used on this processor
ARM subsystem
Not used on this processor
DDR2/mDDR Interface clock source (memory
interface clock is one-half of the value shown)
Optional clock source for ASYNC3 clock domain
peripherals
Alternate clock source input to PLL Controller 0
Bypass clock source for the McASP
Bypass clock source for the USB0
ASYNC Clock Domain (EMIFA)
ASYNC2 Clock Domain (multiple peripherals)
ASYNC3 Clock Domain (multiple peripherals)
1.3V NOM
-
228 MHz
133 MHz
114 MHz
-
456 MHz
-
300 MHz
152 MHz
50 MHz
50 MHz
48 MHz
100 MHz
50 MHz
152 MHz
1.2V NOM
-
187.5 MHz
133 MHz
93.75 MHz
-
375 MHz
-
300 MHz
150 MHz
50 MHz
50 MHz
48 MHz
100 MHz
50 MHz
150 MHz
1.1V NOM
-
100 MHz
100 MHz
50 MHz
-
200 MHz
-
300 MHz
100 MHz
50 MHz
50 MHz
48 MHz
66.6 MHz
50 MHz
100 MHz
1.0V NOM
-
50 MHz
75 MHz
25 MHz
-
100 MHz
-
266 MHz
75 MHz
50 MHz
50 MHz
48 MHz
33.3 MHz
50 MHz
75 MHz
Some interfaces have specific limitations on supported modes/speeds at each operating point. See the
corresponding peripheral sections of this document for more information.
TI provides software components (called the Power Manager) to perform DVFS and abstract the task from
the user. The Power Manager controls changing operating points (both frequency and voltage) and
handles the related tasks involved such as informing/controlling peripherals to provide graceful transitions
between operating points.
74
Peripheral Information and Electrical Specifications
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