AM1806_101 Datasheet, PDF (153/243 Pages) Texas Instruments – ARM Microprocessor

AM1806
www.ti.com
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
Table 6-70. General Timing Requirements for SPI1 Slave Modes⁽¹⁾
NO.
PARAMETER
9 t_c(SPC)S
10 t_w(SPCH)S
11 t_w(SPCL)S
Cycle Time, SPI1_CLK, All Slave Modes
Pulse Width High, SPI1_CLK, All Slave Modes
Pulse Width Low, SPI1_CLK, All Slave Modes
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Setup time, transmit data
12
t_{su(SOMI_SPC)S}
written to SPI before initial
clock edge from
master.^{(3) (4)}
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK rising
13 t_{d(SPC_SOMI)S}
Delay, subsequent bits valid
on SPI1_SOMI after
transmit edge of SPI1_CLK
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK falling
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Output hold time,
14 t_{oh(SPC_SOMI)S} SPI1_SOMI valid after
receive edge of SPI1_CLK
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Polarity = 0, Phase = 0,
to SPI1_CLK falling
Input Setup Time,
15 t_{su(SIMO_SPC)S} SPI1_SIMO valid before
receive edge of SPI1_CLK
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
16 t_{ih(SPC_SIMO)S}
Input Hold Time,
SPI1_SIMO valid after
receive edge of SPI1_CLK
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
1.3V, 1.2V
MIN
40 ⁽²⁾
MAX
256P
18
18
2P
1.1V
MIN
50 ⁽²⁾
MAX
256P
22
22
2P
1.0V
MIN
60 ⁽²⁾
MAX
256P
27
27
UNIT
ns
ns
ns
2P
2P
2P
2P
ns
2P
2P
2P
2P
2P
2P
15
17
19
15
17
19
ns
15
17
19
15
17
19
0.5S-4
0.5S-10
0.5S-12
0.5S-4
0.5S-10
0.5S-12
ns
0.5S-4
0.5S-10
0.5S-12
0.5S-4
0.5S-10
0.5S-12
1.5
1.5
1.5
1.5
1.5
1.5
ns
1.5
1.5
1.5
1.5
1.5
1.5
4
5
6
4
5
6
ns
4
5
6
4
5
6
(1) P = SYSCLK2 period; S = t_c(SPC)S (SPI slave bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 153
Submit Documentation Feedback
Product Folder Link(s): AM1806