AM1806_101 Datasheet, PDF (70/243 Pages) Texas Instruments – ARM Microprocessor

AM1806
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
OSCIN
OSCOUT
NC
OSCV_SS
Clock
Input
to PLL
www.ti.com
Figure 6-7. External 1.2V Clock Source
Table 6-3. OSCIN Timing Requirements for an Externally Driven Clock
PARAMETER
MIN
MAX
UNIT
f_OSCIN
OSCIN frequency range
t_c(OSCIN) Cycle time, external clock driven on OSCIN
t_w(OSCINH) Pulse width high, external clock on OSCIN
t_w(OSCINL) Pulse width low, external clock on OSCIN
t_t(OSCIN) Transition time, OSCIN
t_j(OSCIN) Period jitter, OSCIN
12
20
0.4 t_c(OSCIN)
0.4 t_c(OSCIN)
50
0.25P ⁽¹⁾
0.02P ⁽¹⁾
MHz
ns
ns
ns
ns
ns
(1) Where P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity
on input signals.
6.6 Clock PLLs
The device has two PLL controllers that provide clocks to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device. PLL1 provides clocks to the
mDDR/DDR2 Controller and provides an alternate clock source for the ASYNC3 clock domain. This allows
the peripherals on the ASYNC3 clock domain to be immune to frequency scaling operation on PLL0.
The PLL controller provides the following:
• Glitch-Free Transitions (on changing clock settings)
• Domain Clocks Alignment
• Clock Gating
• PLL power down
The various clock outputs given by the controller are as follows:
• Domain Clocks: SYSCLK [1:n]
• Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
• Post-PLL Divider: POSTDIV
• SYSCLK Divider: D1, ¼, Dn
Various other controls supported are as follows:
• PLL Multiplier Control: PLLM
• Software programmable PLL Bypass: PLLEN
70
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Link(s): AM1806
Copyright © 2010, Texas Instruments Incorporated