AM1806_101 Datasheet, PDF (158/243 Pages) Texas Instruments – ARM Microprocessor

AM1806
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
www.ti.com
Table 6-76. Additional ⁽¹⁾ SPI1 Slave Timings, 5-Pin Option ^{(2) (3)} (continued)
NO.
30 t_{dis(SPC_ENA)S}
PARAMETER
Delay from final clock receive edge on SPI1_CLK to slave
3-stating or driving high SPI1_ENA.⁽⁴⁾
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
1.3V, 1.2V
MIN
MAX
2.5P+15
2.5P+15
2.5P+15
2.5P+15
1.1V
MIN
MAX
2.5P+17
2.5P+17
2.5P+17
2.5P+17
1.0V
MIN
MAX
UNIT
2.5P+19
2.5P+19
ns
2.5P+19
2.5P+19
(4) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should
be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.
158 Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Link(s): AM1806
Copyright © 2010, Texas Instruments Incorporated