AM1806_101 Datasheet, PDF (231/243 Pages) Texas Instruments – ARM Microprocessor

AM1806
www.ti.com
SPRS658B – FEBRUARY 2010 – REVISED MAY 2010
Table 6-121. ARM Debug Features
Category
Hardware Feature
Availability
Software breakpoint
Unlimited
Basic Debug
Hardware breakpoint
Up to 14 HWBPs, including:
2 precise⁽¹⁾ HWBP inside ARM core which are shared with watch points.
8 imprecise⁽¹⁾ HWBPs from ETM’s address comparators, which are shared with trace
function, and can be used as watch points.
4 imprecise⁽¹⁾ HWBPs from ICECrusher.
Up to 6 watch points, including:
Watch point
2 from ARM core which is shared with HWBPs and can be associated with a data.
8 from ETM’s address comparators, which are shared with trace function, and
HWBPs.
Analysis
Watch point with Data
2 from ARM core which is shared with HWBPs.
8 watch points from ETM can be associated with a data comparator, and ETM has
total 4 data comparators.
Counters/timers
3x32-bit (1 cycle ; 2 event)
External Event Trigger In
1
External Event Trigger Out
1
Address range for trace
4
Data qualification for trace
2
System events for trace control
20
Trace Control Counters/Timers for trace control
2x16-bit
State Machines/Sequencers
1x3-State State Machine
Context/Thread ID Comparator
1
Independent trigger control units
12
On-chip Trace
Capture
Capture depth PC
Capture depth PC + Timing
Application accessible
4k bytes ETB
4k bytes ETB
Y
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
6.30.1 JTAG Port Description
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,
TDI, and TDO), a return clock (RTCK) due to the clocking requirements of the ARM926EJ-S and
emulation signals EMU0 and EMU1. TRST holds the debug and boundary scan logic in reset when pulled
low (its default state). Since TRST has an internal pull-down resistor, this ensures that at power up the
device functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST
should be driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be
performed while the TRST pin is pulled low.
PIN
TRST
TYPE
I
TCK
I
RTCK
O
TMS
I
TDI
I
TDO
O
Table 6-122. JTAG Port Description
NAME
Test Logic Reset
Test Clock
Returned Test Clock
Test Mode Select
Test Data Input
Test Data Output
DESCRIPTION
When asserted (active low) causes all test and debug logic in the device to be reset
along with the IEEE 1149.1 interface
This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic.
Depending on the emulator attached to , this is a free running clock or a gated clock
depending on RTCK monitoring.
Synchronized TCK. Depending on the emulator attached to, the JTAG signals are
clocked from RTCK or RTCK is monitored by the emulator to gate TCK.
Directs the next state of the IEEE 1149.1 test access port state machine
Scan data input to the device
Scan data output of the device
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 231
Submit Documentation Feedback
Product Folder Link(s): AM1806