TLC3544_07 Datasheet, PDF (7/42 Pages) Texas Instruments – 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
general electrical characteristics over recommended operating free-air temperature range,
single-ended input, normal long sampling, 200 KSPS, AV_DD = 5 V, external reference (V_REFP = 4 V,
V_REFM = 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00,
analog input signal source resistance = 25 Ω (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN TYP^† MAX UNIT
Resolution
14
bits
Analog Input
Voltage range
0
Reference V
Leakage current
0.01
0.05 µA
Capacitance
30 pF
Reference
Internal reference voltage
3.85
4 4.07 V
Internal reference temperature
coefficient
100
ppm/°C
Internal reference source current
1.8
2.5 mA
Internal reference startup time
20
ms
VREFP
VREFM
External positive reference voltage
External negative reference voltage
External reference input impedance
No conversion (AVDD = 5 V,
CS = DVDD, SCLK = DGND)
Normal long sampling (AVDD = 5 V,
CS = DGND, SCLK = 25 MHz,
External conversion clock)
3
0 AGND
100
8.3 12.5
5V
V
MΩ
kΩ
External reference current
Throughput Rate
No conversion (VREFP = AVDD = 5 V,
VREFM = AGND, External reference,
CS = DVDD)
Normal long sampling (AVDD = 5 V,
CS = DGND, SCLK = 25 MHz external
conversion clock at VREF = 5 V)
1.5
µA
0.4
0.6 mA
f
t(conv)
Internal oscillation frequency
Conversion time
DVDD = 2.7 V to 5.5 V
Internal OSC, 6.5 MHz minute
Conversion clock is external source,
SCLK = 25 MHz (see Note 1)
6.5
2.895
2.785
MHz
µs
Acquisition time
Normal short sampling
1.2
µs
Throughput rate (see Note 2)
Normal long sampling, fixed channel in mode
00 or 01
200
KSPS
DC Accuracy—Normal Long Sampling
EL
Integral linearity error
See Note 3
–1 ±0.5
1 LSB
ED
Differential linearity error
–1 ±0.5
1 LSB
EO
Zero offset error
See Note 4
–3 ±0.6
3 LSB
E(g+)
Gain error
See Note 4
0
5
12 LSB
† _{All typical values are at TA = 25°C.}
NOTES: 1. Conversion time t(conv) = (18x4 / SCLK) + 15 ns.
2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC (refer to Figure 8).
3. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.
4. Zero offset error is the difference between 0000000000000 and the converted output for zero input voltage; gain error is the
difference between 11111111111111 and the converted output for full-scale input voltage. The full-scale input voltage is equal to the
reference voltage being used.
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