TLC3544_07 Datasheet, PDF (22/42 Pages) Texas Instruments – 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
operation cycle timing
CS Initiates
Operation
4 SCLKs
12 SCLKs for Short
44 SCLKs for Long
18 OSC for Internal OSC^†
72 SCLK for External Clock
15 ns
t_(setup)^†
t_(sample)
SDI 4-bit Command 12-bit CFR Data (Optional)
t_(convert)
t_(overhead)
SDO 14-bit Data (Previous Conversion) 2-bit Don’t Care
Active CS (FS Is Tied to High)
CSTAR (For Extended Sampling) occurs at
or after the rising edge of eleventh SCLK
t–CSL to FSL 4 SCLKs
12 SCLKs for Short
44 SCLKs for Long
18 OSC for Internal OSC
72 SCLK for External Clock 15 nS
FS Initiates
Operation
t_(delay)^†
t_(setup)^†
SDI 4-bit Command
t_(sample)
12-bit CFR Data (Optional)
SDO 14-bit Data (Previous Conversion) _{2-bit Don’t Care}
Active CS (CS Can Be Tied to Low)
t_(convert)
t_(overhead)
Active FS
† _{Non JEDEC terms used.}
CSTAR (For Extended Sampling) occurs at
or after the rising edge of eleventh SCLK
After the operation is finished, the host has several choices. Table 3 summarizes operation options.
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