TLC3544_07 Datasheet, PDF (4/42 Pages) Texas Instruments – 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
TLC3544 TLC3548
DESCRIPTION
EOC(INT)
4
4
O End of conversion (EOC) or interrupt to host processor (INT)
EOC: used in conversion mode 00 only. EOC goes from high to low at the end of the sampling and
remains low until the conversion is complete and data is ready.
INT: Interrupt to the host processor. The falling edge of INT indicates data is ready for output. INT
is cleared by the following CS↓, FS↑, or CSTART↓.
FS
REFM
2
2
I Frame sync input from DSP. The rising edge of FS indicates the start of a serial data frame being
transferred (coming into or being sent out of the device). If FS is low at the falling edge of CS, the
rising edge of FS initiates the operation cycle, resets the internal 4-bit counter, and enables SDI,
SDO, and SCLK. Tie this pin to DVDD if FS is not used to initiate the operation cycle.
16
20
I External low reference input. Connect REFM to AGND.
REFP
15
19
I External positive reference input. When an external reference is used, the range of maximum input
voltage is determined by the difference between the voltage applied to this terminal and to the
REFM terminal. Always install decoupling capacitors (10 µF in parallel with 0.1 µF) between REFP
and REFM.
SCLK
1
1
I Serial clock input from the host processor to clock in the input from SDI and clock out the output
via SDO. It can also be used as the conversion clock source when the external conversion clock
is selected (see Table 2). When CS is low, SCLK is enabled. When CS is high, SCLK is disabled
for the data transfer, but can still work as the conversion clock source.
SDI
3
3
I Serial data input. The first 4 MSBs, ID[15:12], are decoded as one 4-bit command. All trailing bits,
except for the CONFIGURE WRITE command, are filled with zeros. The CONFIGURE WRITE
command requires additional 12-bit data. The MSB of input data, ID[15], is latched at the first falling
edge of SCLK following FS falling edge, if FS starts the operation, or latched at the falling edge of
first SCLK following CS falling edge when CS initiates the operation.
SDO
The remaining input data (if any) is shifted in on the rising edge of SCLK and latched on the falling
edge of SCLK. The input via SDI is ignored after the 4-bit counter counts to 16 (clock edges) or a
low-to-high transition of CS, whichever happens first. Refer to the timing specification for the timing
requirements. Tie SDI to DVDD if using hardware default mode (refer to device initialization).
5
5
O The 3-state serial output for the A/D conversion result. All data bits are shifted out through SDO.
SDO is in the high-impedance state when CS is high. SDO is released after a CS falling edge. The
output format is MSB (OD[15]) first.
When FS initiates the operation, the MSB of output via SDO, OD[15], is valid before the first falling
edge of SCLK following the falling edge of FS.
When CS initiates the operation, the MSB, OD[15], is valid before the first falling edge of SCLK
following the CS falling edge.
The remaining data bits are shifted out on the rising edge of SCLK and are valid before the falling
edge of SCLK. Refer to the timing specification for the details.
In a select/conversion operation, the first 14 bits are the results from the previous conversion (data).
In READ FIFO operation, the data is from FIFO. In both cases, the last two bits are don’t care.
In a WRITE operation, the output from SDO is ignored.
SDO goes into high-impedance state at the sixteenth falling edge of SCLK after the operation cycle
is initiated. SDO is in high-impedance state during conversions in modes 01, 10, and 11.
4
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