TLC3544_07 Datasheet, PDF (24/42 Pages) Texas Instruments – 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
operation timing diagrams (continued)
1 23 4 5 6 7
12 13 14 15 16
1
CS
FS = High
ÌÌÌÌÌÌ _SDI
ID15 1D14 ID13 1D12 ID11 ID10 ID9
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ _{ID4 ID3 ID2 ID1 ID0}
ID15 ID14
INT
OR
EOC
SDO
Hi-Z
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ _Note:
Signal May Not Exist.
Don’t Care
ÌÌÌ _{Figure 10. Write Cycle, CS Initiates Operation, FS = 1}
ÌÌÌÌÌÌÌÌ
FIFO Read Operation: When the FIFO is used, the first command after INT is generated is assumed to be the
FIFO read. The first FIFO content is sent out immediately before the command is decoded. If this command is
not a FIFO read, the output is terminated. Using more layers of the FIFO reduces the time taken to read multiple
conversion results, because the read cycle does not generate an EOC or INT, nor does it make a data
conversion. Once the FIFO is read, the entire contents in the FIFO must be read out. Otherwise, the remaining
data is lost.
1234567
12 13 14 15 16
1
SCLK
CS
FS = High
ÌÌÌÌÌÌ SDI
ID15
1D14
ID13
1ÌÌD12 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌID15
ID14
INT
OR
EOC
SDO
OD15 OD14 OD13 OD12 OD11 OD10 OD9
ÌÌÌÌÌÌÌÌ OD4 OD3 OD2
Hi-Z
Notes:
Signal May Not Exist.
OD[15:2] is FIFO Contents.
ÌÌÌÌ _{Don’t Care}
Figure 11. FIFO Read Cycle, CS Initiates Operation, FS = 1
OD15 OD14
24
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