TLC3544_07 Datasheet, PDF (28/42 Pages) Texas Instruments – 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
conversion operation (continued)
Configure Conversion
From CH0
CS
Conversion
From CH2
Conversion
From CH0
Conversion
From CH2
FS
CSTART
Ì^SDI
***
*_Ì* _{ÌÌÌÌÌÌÌÌÌÌ}* _ÌÌ* _ÌÌ* _Ì*
**_{ÌÌÌÌÌÌÌÌÌ}* _Ì
INT
SDO
1st SWEEP
ÌÌÌÌÌ_{Don’t Care}
ÌÌ*** Command = Configure Write for Mode 11, FIFO
Threshold = 1/2 Full, Sweep Sequence: 0–0–2–2
** COMMAND = Select Any Channel
* COMMAND = Read FIFO
CH0
CH0
CH2
1st FIFO Read
ÌÌ ^CH2
Read FIFO After 1st SWEEP Completed
REPEAT
CH0
2nd FIFO Read
Possible Signal
Figure 20. Mode 11, CSTART Triggers Samplings/Conversions
conversion clock and conversion speed
The conversion clock source can be the internal OSC, or the external clock SCLK. When the external clock is
used, the conversion clock is equal to SCLK/4. It takes 18 conversion clocks plus 15 ns to finish the conversion.
If the external clock is selected, the conversion time (not including sampling time) is 18X(4/f_SCLK)+15 ns. Table 4
shows the maximum conversion rate (including sampling time) when the analog input source resistor is 1 kΩ.
DEVICE
TLC3544/48
(Rs = 1000)
Table 4. Maximum Conversion Rate
SAMPLING MODE
CONVERSION CLK
Short (16 SCLK)
Long (48 SCLK)
Short (16 SCLK)
Long (48 SCLK)
External SCLK/4
External SCLK/4
Internal 6.5 MHz
Internal 6.5 MHz
MAX SCLK
(MHz)
10
25
10
25
CONVERSION
TIME (us)
8.815
4.815
4.385
4.705
RATE
(KSPS)
113.4
207.7
228
212.5
FIFO operation
ADC
×8
FIFO
Serial
SOD
76543210
FIFO Full
FIFO 1/2 Full
FIFO 3/4 Full
FIFO 1/4 Full
FIFO Threshold Pointer
Figure 21. FIFO Structure
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