TLC3544_07 Datasheet, PDF (12/42 Pages) Texas Instruments – 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
timing requirements over recommended operating free-air temperature range, AV_DD = 5 V,
DV_DD = 5 V, V_REFP = 5 V, V_REFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
FS trigger
td(8)
tsu(3)
tw(3)
td(9)
PARAMETERS
Delay time, delay from CS falling edge to FS rising edge, at 25-pF load
Setup time, FS rising edge before SCLK falling edge, at 25-pF load
Pulse width, FS high at 25-pF load
Delay time, delay from FS rising edge to MSB of SDO valid
(reaches 90% final level) at 10-pF load
DVDD = 5 V
DVDD = 2.7 V
td(10) Delay time, delay from FS rising edge to next FS rising edge at 25-pF load
td(11)
Delay time, delay from FS rising edge to INT rising edge at
10-pF load
† _{Specified by design}
DVDD = 5 V
DVDD = 2.7 V
MIN
0.5
0.25×tc(1)
0.75×tc(1)
Required
sampling time +
conversion time
0
TYP
MAX
tc(1)
0.5×tc(1)+5
1.25×tc(1)
26^†
30^†
UNIT
tc(1)
ns
ns
ns
µs
6^†
16^{† ns}
td(10)
VIH
CS
VIL
td(8)
tw(3)
FS
SCLK
tsu(3)
1
16
SDI
Don’t Care
ID15 ID1
ID0
Don’t Care
ID15
Don’t Care
td(9)
SDO
Hi-Z
OD15
OD1 OD0
Hi-Z
OD15
Don’t Care
EOC
OR
INT
VOH
VOH
td(11)
NOTE A: – – – – The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, FS initiates the conversion, CS can be tied to low. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK, SDI)
are inactive and are ignored.
Parts with date code earlier than 13XXXXX have these discrepancies:
(Date code is a 7 digit code next to the TI where the first digit indicates the year and the second digit is the month of production. 13,
in this case, is 2001 and the month of March.)
SDO MSB (OD[15]) comes out from the falling edge of CS instead of FS rising edge in DSP mode (FS triggered).
Figure 3. Critical Timing for FS Trigger
12
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