OMAP-L137 Datasheet, PDF (67/219 Pages) Texas Instruments – Low-Power Applications Processor

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OMAP-L137 Low-Power Applications Processor
SPRS563A – SEPTEMBER 2008 – REVISED OCTOBER 2008
4.4.3 CFGCHIP2
31
30
29
28
27
26
25
24
RESERVED
R-n/a
23
22
21
20
19
18
17
16
RESERVED
USB0PHYCLKGD USB0VBUSSENSE
R-n/a
15
RESET
R/W-1
14
13
12
USB0OTGMODE
USB1PHYCLKMUX
R/W-11
R/W-0
11
USB0PHYCLKMUX
R/W-1
10
9
8
USB0PHYPWDN USB0OTGPWRDN USB0DATPO
L
R/W-1
R/W-1
R/W-1
7
USB1SUSPENDM
R/W-0
6
USB0PHY_PLLON
R/W-0
5
4
3
USB0SESNDEN USB0VBDTCTEN
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
1
0
USB0REF-FREQ[3:0]
R/W-0000
Figure 4-26. CFGCHIP2 Register Bit Layout
Bit
31:8
17
16
15
14:13
12
11
10
9
8
7
6
5
4
Field
Reserved
USB0PHYCLKGD
USB0VBUSSENSE
Reset
USB0OTGMODE
USB1PHYCLKMUX
USB0PHYCLKMUX
USB0PHYPWDN
USB0OTGPWRDN
USB0DATPOL
USB1SUSPENDM
USB0PHY_PLLON
USB0SESNDEN
USB0VBDTCTEN
Table 4-27. CFGCHIP2 Field Description
Description
Reserved
Indicates clock is present, power is good and phy PLL is locked.
Indicates status of VBUS detection.
When '1' drives 'phy_reset' active to put the phy UTMI+ interface in reset.
OTGMODE = 00. Do not override phy values. Let PHY drive signals to controller based
on its comparators for the VBUS and ID pins.
OTGMODE = 01. Override phy values to force USB Host Operation.
Force VBUSVALID = 1, SESSVALID = 1, SESSEND = 0, IDDIG = 0
OTGMODE = 10. Override phy values to force USB Device Operation.
Force VBUSVALID = 1, SESSVALID = 1, SESSEND = 0, IDDIG = 1
OTGMODE = 11. Override phy values to force USB Host Operation with VBUS low.
Force VBUSVALID = 0, SESSVALID = 0, SESSEND = 1, IDDIG = 0
USB1 PHY Clock Source.
1 = USB1 Phy Clock (48 MHz) is sourced by an external pin.
0 = USB1 Phy Clock (48 MHz) is sourced by the 48 MHz output of the USB0 PHY.
USB0 PHY Clock Source.
1 = USB0 Phy reference clock internally generated.
0 = USB0 Phy reference clock comes from pin.
Phy Powerdown 0=Phy is powered up, 1=Phy is powered down.
OTG Analog Module Powerdown 0=OTG Analog Module is powered up, 1=OTG Analog
Module is powered down.
USB0 Data Polarity, 0 = Reversed DP/DM polarity, 1 = Normal DP/DM polarity.
USB1 Phy Suspend, Program to '0' if USB1 is not used, Program to '1' if USB1 is used.
USB0 Phy PLL On, 0 = Normal USB Behavior, 1 = Override USB SUSPEND behavior
and release PLL from SUSPEND state.
Turns on session end comparator.
Turns on all VBUS line comparators.
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Device Configuration
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