OMAP-L137 Datasheet, PDF (137/219 Pages) Texas Instruments – Low-Power Applications Processor

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OMAP-L137 Low-Power Applications Processor
SPRS563A – SEPTEMBER 2008 – REVISED OCTOBER 2008
Table 6-43. McASP0 Switching Characteristics⁽¹⁾
NO.
9
t_c(AHCLKRX)
10
t_w(AHCLKRX)
11
t_c(ACLKRX)
12
t_w(ACLKRX)
13
t_{d(ACLKRX-AFSRX)}
14
t_{d(ACLKX-AXRV)}
15
t_{dis(ACLKX-AXRHZ)}
PARAMETER
Cycle time, AHCLKX0 internal, AHCLKR0 output
Cycle time, AHCLKR0 external, AHCLKR0 output
Cycle time, AHCLKX0 internal, AHCLKX0 output
Cycle time, AHCLKX0 external, AHCLKX0 output
Pulse duration, AHCLKR0 internal, AHCLKR0
output
Pulse duration, AHCLKR0 external, AHCLKR0
output
Pulse duration, AHCLKX0 internal, AHCLKX0
output
Pulse duration, AHCLKX0 external, AHCLKX0
output
Cycle time, ACLKR0 internal, ACLKR0 output
Cycle time, ACLKR0 external, ACLKR0 output
Cycle time, ACLKX0 internal, ACLKX0 output
Cycle time, ACLKX0 external, ACLKX0 output
Pulse duration, ACLKR0 internal, ACLKR0 output
Pulse duration, ACLKR0 external, ACLKR0 output
Pulse duration, ACLKX0 internal, ACLKX0 output
Pulse duration, ACLKX0 external, ACLKX0 output
Delay time, ACLKR0 internal, AFSR output⁽⁷⁾
Delay time, ACLKX0 internal, AFSR output⁽⁸⁾
Delay time, ACLKX0 internal, AFSX output
Delay time, ACLKR0 external input, AFSR output⁽⁷⁾
Delay time, ACLKX0 external input, AFSR output⁽⁸⁾
Delay time, ACLKX0 external input, AFSX output
Delay time, ACLKR0 external output, AFSR
output ⁽⁷⁾
Delay time, ACLKX0 external output, AFSR
output ⁽⁸⁾
Delay time, ACLKX0 external output, AFSX output
Delay time, ACLKX0 internal, AXR0[n] output
Delay time, ACLKX0 external input, AXR0[n] output
Delay time, ACLKX0 external output, AXR0[n]
output
Disable time, ACLKX0 internal, AXR0[n] output
Disable time, ACLKX0 external input, AXR0[n]
output
Disable time, ACLKX0 external output, AXR0[n]
output
MIN
20
20
20
20
(AHR/2) – 2.5⁽²⁾
(AHR/2) – 2.5⁽²⁾
(AHX/2) – 2.5⁽³⁾
(AHX/2) – 2.5⁽³⁾
greater of 2P or 20 ns⁽⁴⁾
greater of 2P or 20 ns⁽⁴⁾
greater of 2P or 20 ns⁽⁴⁾
greater of 2P or 20 ns⁽⁴⁾
(AR/2) – 2.5⁽⁵⁾
(AR/2) – 2.5⁽⁵⁾
(AX/2) – 2.5⁽⁶⁾
(AX/2) – 2.5⁽⁶⁾
0
0
0
3
3
3
3
3
3
0
3
3
0
3
3
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR0.
(3) AHX - Cycle time, AHCLKX0.
(4) P = SYSCLK2 period
(5) AR - ACLKR0 period.
(6) AX - ACLKX0 period.
(7) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(8) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
MAX UNIT
ns
ns
ns
ns
5.8
5.8
5.8
11.6
11.6
11.6
ns
11.6
11.6
11.6
5.8
11.6
ns
11.6
5.8
11.6
ns
11.6
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Peripheral Information and Electrical Specifications 137