TMS320C6424 Datasheet, PDF (6/243 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347A – MARCH 2007 – REVISED APRIL 2007
Revision History
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This data manual revision history highlights the technical changes made to the SPRS347 device-specific
data manual to make it an SPRS347A revision.
Scope: Applicable updates to the C642x DSP device family, specifically relating to the TMS320C6424
device, have been incorporated.
Upon exit from the bootloader code, all C64x+ memories are configured as all RAM, Cache is disabled.
For proper C6424 device operation, clock ratio requirements must be met for the following peripheral
electrical data/timings: McASP0, EMAC (MII/RMII Operation), and PCI.
SEE
Global
Global
Section 2.2.2
Section 3.4.1
Section 3.6.1
Section 3.7.2.2
Section 3.7.3.8
Section 3.8
Section 6.5.1
Section 6.4.2
Section 6.10.2
ADDITIONS/MODIFICATIONS/DELETIONS
Updated/Changed "DSP Subsystem" to "DSP"
General-Purpose Input/Output (GPIO) pins shall be referred to as GP[x]. Register bit fields and interrupt
acronyms may be different (e.g., GPIO01 interrupt)
Section 2.2.2, C64x+ Memory Architecture:
Table 2-2, C64x+ Cache Registers:
Added device-specific information relating to L1P, L1D, and L2 memory regions/ports.
Added "... (corresponds to byte address ...)" to MAR0 through MAR255 register DESCRIPTIONs for
clarification
Section 3.4.1, Boot Modes:
Internal Bootloader ROM (0x0010 0000) bullet:
Updated/Changed Note: sentence from "If cache use if required, ..." to "If cache use is required, ..."
Section 3.6.1, Switch Central Resource (SCR) Bus Priorities:
Added Table 3-12, MSTPRI0 Register Bit Description
Added Table 3-13, MSTPRI1 Register Bit Description
Section 3.7.2.2, PINMUX1 Register Description:
Figure 3-12, PINMUX1 Register:
Updated/Changed the LEGEND for Bit 0, "PCIEN" from "R/W-P" to "R-P".
Table 3-18, PINMUX1 Register Bit Descriptions:
Added the "The PCIMUX.PCIEN reflects the state of the PCIEN ..." paragraph to the Bit 0, PCIEN
description.
Section 3.7.3.8, Timer0 Block:
Added "GPIO" to the "This block of 2 pins consists of ... muxed pins." paragraph.
Section 3.8, Device Initialization Sequence After Reset:
Added "TMS320C642x DSP DDR2 Memory Controller User's Guide (literature number SPRUEM4)"
reference to step 8.b. in the "Special Considerations:" paragraph.
Section 6.5.1, Power-on Reset (POR Pin), Step 5.:
Updated/Changed the document reference to Using the TMS320C642x Bootloader Application Report
(literature number SPRAAK5).
Section 6.4.2, EDMA Peripheral Register Description(s):
Table 6-7, C6424 EDMA Registers:
Added 0x01C0 0608 "QSTAT2" "Queue 2 Status Register"
Added "Command" to the register name for all RDRATE registers
Deleted "Source" from all SABIDX register names
Updated/Changed "BIDX" to "B-Index" for all DFBIDX0 through DFBIDX3 register names
Section 6.10.2, UART Electrical Data/Timing:
Updated parameter signal names to "UTXDx" and "URXDx"
Updated signal names in Figure 6-19, UARTx Transmit/Receive Timing
6
Revision History
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