TMS320C6424 Datasheet, PDF (49/243 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347A – MARCH 2007 – REVISED APRIL 2007
Table 2-17. VLYNQ Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
VLYNQ
VLYNQ_CLOCK/
PCICLK/GP[57]
A7
A8
I/O/Z
HD0/VLYNQ_SCRUN/
AD18/GP[58]
C8
B9
I/O/Z
IPU
DV_DD33
IPU
DV_DD33
This pin is multiplexed between VLYNQ, PCI, and GPIO.
For VLYNQ, it is the clock VLYNQ_CLOCK [I/O/Z].
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is the Serial Clock run request VLYNQ_SCRUN
[I/O/Z].
HD8/VLYNQ_TXD3/
PPERR/GP[66]
A5
HD7/VLYNQ_TXD2/
PDEVSEL/GP[65]
B6
HD6/VLYNQ_TXD1/
PTRDY/GP[64]
D6
HD5/VLYNQ_TXD0/
PIRDY/GP[63]
A6
HD4/VLYNQ_RXD3/
PFRAME/GP[62]
C7
HD3/VLYNQ_RXD2/
PCBE2/GP[61]
B7
HD2/VLYNQ_RXD1/
AD17/GP[60]
A8
HD1/VLYNQ_RXD0/
AD16/GP[59]
D7
A6
I/O/Z
B7
I/O/Z
C7
I/O/Z
A7
I/O/Z
C8
I/O/Z
B8
I/O/Z
A9
I/O/Z
C9
I/O/Z
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3.
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2.
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1.
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is transmit bus bit 0 output VLYNQ_TXD0.
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3.
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2.
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1.
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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