TMS320C6424 Datasheet, PDF (175/243 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347A – MARCH 2007 – REVISED APRIL 2007
6.9.4 DDR2 Memory Controller
The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A
standard compliant DDR2 SDRAM Devices and can interface to either 16-bit or 32-bit DDR2 SDRAM
devices. For details on the DDR2 Memory Controller, see the TMS320C642x DSP Peripherals Overview
Reference Guide (literature number SPRUEM3) and the TMS320C642x DSP DDR2 Memory Controller
User's Guide (literature number SPRUEM4).
A memory map of the DDR2 Memory Controller registers is shown in Table 6-26.
Table 6-26. DDR2 Memory Controller Registers
HEX ADDRESS RANGE
0x01C4 004C
0x01C4 2038
0x2000 0000 - 0x2000 0003
0x2000 0004
0x2000 0008
0x2000 000C
0x2000 0010
0x2000 0014
0x2000 0020
0x2000 0024 - 0x2000 00BF
0x2000 00C0
0x2000 00C4
0x2000 00C8
0x2000 00CC
0x2000 00D0 - 0x2000 00E3
0x2000 00E4
0x2000 00E8 - 0x2000 00EF
0x2000 00F0
0x2000 00E8 - 0x2000 7FFF
ACRONYM
DDRVTPER
DDRVTPR
-
SDRSTAT
SDBCR
SDRCR
SDTIMR
SDTIMR2
PBBPR
-
IRR
IMR
IMSR
IMCR
-
DDRPHYCR
-
VTPIOCR
-
REGISTER NAME
DDR2 VTP Enable Register
DDR2 VTP Register
Reserved
SDRAM Status Register
SDRAM Bank Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register
SDRAM Timing Register 2
Peripheral Bus Burst Priority Register
Reserved
Interrupt Raw Register
Interrupt Masked Register
Interrupt Mask Set Register
Interrupt Mask Clear Register
Reserved
DDR PHY Control Register
Reserved
DDR VTP IO Control Register
Reserved
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Peripheral Information and Electrical Specifications 175