TMS320C6424 Datasheet, PDF (53/243 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347A – MARCH 2007 – REVISED APRIL 2007
Table 2-21. Multichannel Audio Serial Port (McASP0) Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
McASP0
AMUTEIN0/FSX1/
GP[109]
F2
G3
I/O/Z
AMUTE0/DR1/
GP[110]
G3
H3
I/O/Z
ACLKR0/CLKX0/
GP[99]
H1
J1
I/O/Z
AHCLKR0/CLKR0/
GP[101]
J2
K1
I/O/Z
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 mute input AMUTEIN0 (I).
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 mute output AMUTE0 (O/Z).
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 receive bit clock ACLKR0 (I/O/Z).
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 receive high-frequency master clock
AHCLKR0 (I/O/Z).
ACLKX0/CLKX1/
GP[106]
F1
G1
I/O/Z
AHCLKX0/CLKR1/
GP[108]
G1
H1
I/O/Z
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 transmit bit clock ACLKX0 (I/O/Z).
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 transmit high-frequency master clock
AHCLKX0 (I/O/Z).
AFSR0/DR0/
GP[100]
H4
K3
I/O/Z
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 receive frame synchronization AFSX0
(I/O/Z).
AFSX0/DX1/
GP[107]
G2
G2
I/O/Z
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 transmit frame synchronization AFSR0
(I/O/Z).
AXR0[3]/FSR0/
GP[102]
G4
J3
I/O/Z
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 3
AXR0[3] (I/O/Z).
AXR0[2]/FSX0/
GP[103]
H3
J2
I/O/Z
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 2
AXR0[2] (I/O/Z).
AXR0[1]/DX0/
GP[104]
J3
K2
I/O/Z
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 1
AXR0[1] (I/O/Z).
AXR0[0]/FSR1/
GP[105]
H2
H2
I/O/Z
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 0
AXR0[0] (I/O/Z).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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