TMS320C6424 Datasheet, PDF (199/243 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347A – MARCH 2007 – REVISED APRIL 2007
Table 6-49. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1⁽¹⁾⁽²⁾
(see Figure 6-32)
-400
-500
NO.
-600
UNIT
MASTER
SLAVE
MIN
MAX
MIN
MAX
4
t_su(DRV-CKXH)
5
t_h(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
14
2 - 3P
ns
4
5+ 6P
ns
(1) P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10ns.
(2) For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
Table 6-50. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 1⁽¹⁾⁽²⁾ (see Figure 6-32)
NO.
PARAMETER
MASTER ⁽³⁾
-400
-500
-600
SLAVE
UNIT
MIN
MAX
MIN
MAX
1
t_h(CKXH-FXL)
2
t_d(FXL-CKXL)
3
t_d(CKXH-DXV)
6
t_{dis(CKXH-DXHZ)}
Hold time, FSX low after CLKX high⁽⁴⁾
Delay time, FSX low to CLKX low⁽⁵⁾
Delay time, CLKX high to DX valid
Disable time, DX high impedance following
last data bit from CLKX high
H-4
T-2
-4
-6
H + 5.5
T+1
5.5
7.5
3P + 2.8
3P + 2
ns
ns
5P + 17 ns
5P + 17 ns
7
t_d(FXL-DXV)
Delay time, FSX low to DX valid
L-2
L+ 4
2P + 2
4P + 17 ns
(1) P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10ns.
(2) For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
(3) S = Sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK3 period)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
FSX
6
DX
Bit 0
DR
Bit 0
2
7
Bit(n-1)
4
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
Figure 6-32. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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Peripheral Information and Electrical Specifications 199