TMS320C6424 Datasheet, PDF (151/243 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347A – MARCH 2007 – REVISED APRIL 2007
During this time, the following happens:
– The reset signals flow to the entire chip resetting all the modules on chip except the emulation
logic.
– The PLL Controllers are reset thereby, switching back to PLL Bypass Mode and resetting all their
registers to default values. Both PLL1 and PLL2 are placed in reset and lose lock.
– The RESETOUT pin becomes asserted (low), indicating the device is in reset.
2. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles. At the
end of these 10 cycles, the RESETOUT pin is deasserted (driven high).
At this point:
– The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX0 and PINMUX1 registers).
– The clock and reset of each peripheral is determined by the default settings of the Power and Sleep
Controller (PSC).
– The PLL Controllers are operating in PLL Bypass Mode.
– The C64x+ begins executing from DSPBOOTADDR (determined by bootmode selection).
After the reset sequence, the boot sequence begins. Since the boot and configuration pins are not latched
with a Max Reset, the previous values (as shown in the BOOTCFG register) are used to select the boot
mode. For more details, see the Using the TMS320C642x Bootloader Application Report (literature
number SPRAAK5).
After the boot sequence, follow the software initialization sequence described in Section 3.8, Device
Initialization Sequence After Reset.
6.5.4 CPU Local Reset
The C64x+ DSP CPU has an internal reset input that allows a host (PCI/HPI) to control it. This reset is
configured through a register bit (MDCTL[39].LRST) in the Power Sleep Controller (PSC) module. When in
C64x+ local reset, the slave DMA port on C64x+ will remain active and the internal memory will be
accessible. For procedures on asserting and de-asserting CPU local reset by the host, see TMS320C642x
Power and Sleep Controller (PSC) Reference Guide (literature number SPRUEN8).
For information on peripheral selection at the rising edge of POR or RESET, see Section 3, Device
Configurations of this data manual.
6.5.5 Peripheral Local Reset
The user can configure the local reset and clock state of a peripheral through programming the PSC.
Table 6-4, C6424 LPSC Assignments identifies the LPSC numbers and the peripherals capable of being
locally reset by the PSC. For more detailed information on the programming of these peripherals by the
PSC, see the TMS320C642x Power and Sleep Controller (PSC) Reference Guide (literature number
SPRUEN8).
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Peripheral Information and Electrical Specifications 151