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CDCE421 Datasheet, PDF (6/30 Pages) Texas Instruments – Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator
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CDCE421
SCAS842 – APRIL 2007
www.ti.com
Enter Programming Mode
Figure 3 shows the timing behavior of data to be written into SDATA. The sequence shown is 00 1100. If the
high period is as short as t1, this is interpreted as 0. If the high period is as long as t3, this is interpreted as a 1.
This behavior is achieved by shifting the incoming signal SDATA by time t5 into signal SDATA_DELAYED. As
can be seen in Figure 3, SDATA_DELAYED can be used to latch (or strobe) SDATA. The timing specifications
for t1–t7, tr, and tf are shown in Figure 3.
t7
CE
t6
t2
t4
t1
tf
t3
tr
SDATA
t5
SDATA
DELAYED
DATA
0
0
1
fSDATACLK
t1
t2
t2
t3
t4
t4
t6
Repeat frequency of programming
LOW signal: high-pulse duration
LOW signal: low-pulse duration while entering programming sequence
LOW signal: low-pulse duration while programming bits
HIGH signal: high-pulse duration
HIGH signal: low-pulse duration while entering programming sequence
HIGH signal: low-pulse duration while programming bits
Time-out during Entering Programming Mode and Enter Read Back Mode
until next bit must turn on
t7
CE-high time before first SDATA can be clocked in
tr and tf
Rise Time and Fall Time
t = 1 / fSDATACLK
Figure 3. SDATA/CE Timing
1
0
MIN TYP MAX
60
70
80
0.2 t
0.8 t
0.8 t
0.8 t
0.2 t
0.2 t
16
3t
2
0
T0042-05
UNIT
kHz
ms
ms
ms
ms
ms
ms
µs
ms
ns
EEPROM PROGRAMMING
Load all the registers in RAM by writing Word0 through Word5, and after going back to State 2, then going to
State 3 (programming EEPROM, no locking) or State 4 (programming EEPROM with locking), the contents of
Word0–Word5 are saved in the EEPROM. Wait 10 ms in State 3 or State 4 when programming the EEPROM
before moving to State 2 (the idle state).
NOTE:
When writing to the device for functionality testing and verification via the serial bus,
only the RAM is being accessed.
6
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