CDCE421 Datasheet, PDF (16/30 Pages) Texas Instruments – Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator

CDCE421
SCAS842 – APRIL 2007
www.ti.com
For the case of a CDCE421 being referenced by an external and cleaner LVCMOS input of 35.42 MHz, Figure 8
shows the SSB phase noise plot of the output at 708 MHz from 100 Hz to 40 MHz from the carrier. Note the
dependence of output jitter on the input reference jitter. See Figure 13 for test setup.
0
−20
−40
−60
−80
−100
−120
−140
−160
10
100
1k
10k
100k
1M
10M
f − Single-Sideband Frequency − Hz
Figure 8. Phase Noise Plot for LVPECL Output at 708 MHz
100M
G001
Table 5. Phase Noise Parameters With LVCMOS Input of 35.4 MHz and LVPECL Output at 708 MHz
Phase noise specifications under following assumptions: input frequency f = 35.42 MHz (VCO = 2, prescaler = 3, output divider =
1), f_out = 708 MHz (driver mode = LVPECL)
PARAMETER
MIN
TYP MAX UNIT
phn₁₀₀
phn_1k
phn_10k
phn_100k
phn_1M
phn_10M
phn_20M
J_RMS
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
–95
–105
–109
–114
–126
–146
–146
438
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
16
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