CDCE421 Datasheet, PDF (12/30 Pages) Texas Instruments – Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator

CDCE421
SCAS842 – APRIL 2007
www.ti.com
PACKAGE (QFN24)
The CDCE421 is also packaged in a QFN 24-pin package. The QFN package footprint is shown. Pad locations
and numbers are shown in Figure 6.
RGE PACKAGE
(TOP VIEW)
CE 1
NC 2
SDATA 3
NC 4
NC 5
NC 6
CDCE421
18 NC
17 VCC
16 VCC
15 NC
14 NC
13 NC
P0024-05
Figure 6. Pinout of the CDCE421 QFN-24 Package
PIN DESCRIPTION
Table 3 shows the pin description for the CDCE421 QFN-24 Package.
TERMINAL
NAME
CE
GND
No connect
OUTN
OUTP
SDATA
VCC
XIN 1
XIN 2
TERMINAL
NO.
1
8, 9
2, 4–6,
11–15,
18–20, 23,24
7
10
3
16, 17
21
22
Table 3. Pinout Description of CDCE421
TYPE
I
GND
ESD
Protection
Y
Y
Description
Chip enable
CE = 1: enable the device and the outputs.
CE = 0: disable all current sources; in LVDS mode, LVDSP = LVDSN = Hi-Z;
in LVPECL mode, LVPECLP = LVPECLN = Hi-Z.
Ground
Do not connect these pins. Leave them floating.
O
O
I
Power
I
GND
Y
High-speed negative differential LVPECL or LVDS outputs. (Outputs are
enabled by CE and selected by the EEPROM configuration registers.)
Y
High-speed positive differential LVPECL or LVDS outputs. (Outputs are
enabled by CE and selected by the EEPROM configuration registers.)
Y
Programming pin using TI proprietary interface protocol
Y
3.3-V power supply
Y
In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the
N
other end of the crystal. In LVCMOS input single-ended driven mode, XIN1
(pin 21) acts as input reference and XIN2 should connect to GND.
12
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