CDCE421 Datasheet, PDF (4/30 Pages) Texas Instruments – Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator

CDCE421
SCAS842 – APRIL 2007
www.ti.com
DEVICE SETUP EXAMPLE
The following example illustrates the procedure to calculate the required AT-cut crystal frequency needed to
generate a desired output frequency.
Assuming the requirement to generate an output frequency of 622.08 MHz, Table 1 shows that the desired
output frequency lies between 583.5 and 680 MHz.
DESIRED OUTPUT
FREQUENCY (MHz)
From
650.0
583.5
510.0
To
766.7
650.0
587.5
REQUIRED INPUT
CRYSTAL
FREQUENCY (MHz)
From
To
32.500
38.333
29.174
32.500
31.875
36.719
VCO
SELECTION
VCO 2
VCO 1
VCO 2
OUTPUT
DIVIDER
1
1
1
PRESCALER
SETTING
3
3
4
FEEDBACK
DIVIDER ⁽¹⁾
20
20
16
(1) The feedback divider is set automatically with respect to the prescaler setting.
So this means that the device must be configured with:
VCO = VCO 1
Output divider = 1
Prescaler setting = 3
To determine the right crystal frequency needed to get 622.08 MHz with these settings, substitute values into
Equation 1.
ǒ Ǔ ǒ Ǔ ^{OutputDivider}
f_xtal + _{FeedbackDivider}
f_out
f_xtal +
1
20
622.08 + 31.154 MHz
(2)
The AT-cut frequency should be 31.154 MHz (between 29.174 MHz and 32.500 MHz. as shown in Table 1) .
SERIAL INTERFACE AND CONTROL
The CDCE421 uses a unique Texas Instruments proprietary interface protocol that can be configured and
programmed via a single input pin to the device. The architecture enables only writing to the device from this
input pin. Reading the content of a register can be achieved by sending a read command on the input pin and
monitoring the output pins (LVDS or LVPECL). In a case where the output pins cannot be used to read the
content, the software controlling the interface must account for what is written to the EEPROM and when it is
programmed. Monitoring the outputs verifies the programming modes, and cycling power on the device verifies
that the EEPROM is holding the proper configuration.
The CDCE421 can be configured and programmed via the SDATA input pin. For this purpose, a square-wave
programming sequence must be written to the device as described in the following section. During the EEPROM
programming phase, the device requires a stable V_CC of 3.3 V ± 100 mV for secure writing of the EEPROM
cells. After each Write to WordX, the written data is latched, made effective, and offers look-ahead before the
actual data is stored into the EEPROM.
The following table summarizes all valid programming commands.
SDATA
00 1100
11 1011
000 xxxx xxxx
100 xxxx xxxx
010 xxxx xxxx
110 xxxx xxxx
FUNCTION
Enter Programming Mode (State 1 → State 2); bits must be sent in the specified order with the specified timing.
Otherwise, a time-out occurs.
Enter Register Read Back Mode; bits must be sent in the specified order with the specified timing. Otherwise, a
time-out occurs.
Write to Word0 (State 2)^(1)(2)(3)
Write to Word1 (State 2)^{(1) (2) (3)}
Write to Word2 (State 2)^{(1) (2) (3)}
Write to Word3 (State 2)^{(1) (2) (3)}
(1) Each rising edge causes a bit to be latched.
(2) Between the bits, some longer time delays can occur, but this has no effect on the data.
(3) A Write to WordX is expected to be 10 bits long. After the 10^th bit, the respective word is latched and its effect can be observed as
look-ahead function.
4
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