CDCE421 Datasheet, PDF (13/30 Pages) Texas Instruments – Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator

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CDCE421
SCAS842 – APRIL 2007
OUTPUTS (LVPECL OR LVDS)
The CDCE421 device has two sets of output drivers, LVPECL and LVDS, where the outputs are wire-ORed
together. Only one output can be selected at a time; the other goes to the high-impedance state (Hi-Z).
If the device is configured for an LVPECL, the output buffers go to Hi-Z and the termination resistors determine
the state of the output (LVPECLP = LVPECLN = Hi-Z) in the device disable mode (CE = L). If the device is
configured in LVDS mode, the outputs go to Hi-Z if the device is disabled (CE = L).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) ⁽¹⁾
V_CC
Supply voltage⁽²⁾
V_I
Voltage range for all other input pins⁽²⁾
I_O
Output current for LVPECL
Electrostatic discharge (HBM)
T_A
Characterized free-air temperature range (no airflow)
T_J
Maximum junction temperature
T_stg
Storage temperature range
VALUE
–0.5 to 4.6
–0.5 to V_CC + 0.5
–50
2
–40 to 85
125
–65 to 150
UNIT
V
V
mA
kV
°C
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
V_CC
Supply voltage
T_A
Ambient temperature (no airflow, no heat sink)
MIN
TYP
MAX UNIT
3
3.3
3.6 V
–40
85 °C
ELECTRICAL CHARACTERISTICS
recommended operating conditions for CDCE421 device
PARAMETER
V_CC
Supply voltage
I_VCC(LVDS) Total current
I_VCC(LVPECL) Total current consumption
LVDS OUTPUT MODE (see Figure 10)
f_CLK
|V_OD|
∆V_OD
V_OS
∆V_OS
t_r
t_f
Output frequency
LDVS differential output voltage
LVDS VOD magnitude change
Offset voltage
VOS magnitude change
Output rise time
Output fall time
I_OS
Duty cycle of the output waveform
TEST CONDITIONS
LVDS mode, 3.3 V, 366 MHz
LVPECL mode, 3.3 V, 366 MHz
R_L = 100 Ω
–40°C to 85°C
20% to 80% of V_OUTpp
80% to 20% of V_OUTpp
Short V_out+ to ground
Short V_out– to ground
MIN TYP
3
3.3
73
91
10.9
240
400
0.84
1.1
170
170
46% 50%
MAX
3.6
93
110
UNIT
V
mA
mA
400
454
50
1.39
25
–20
20
53%
MHz
mV
mV
V
mV
ps
ps
mA
mA
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