CDCE421 Datasheet, PDF (17/30 Pages) Texas Instruments – Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator

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CDCE421
SCAS842 – APRIL 2007
For the case of CDCE421 being referenced by a clean external LVCMOS input of 33.33 MHz, Figure 9 shows
the SSB phase noise plot of the output at 400 MHz from 100 Hz to 40 MHz from carrier. See Figure 12 for test
setup.
0
−20
−40
−60
−80
−100
−120
−140
−160
10
100
1k
10k
100k
1M
10M
f − Single-Sideband Frequency − Hz
Figure 9. Phase Noise Plot for LVDS Output at 400 MHz
100M
G002
Table 6. Phase Noise Parameters With LVCMOS Input of 33.33 MHz and LVDS Output at 400 MHz
Phase noise specifications under following assumptions: input frequency f = 33.33 MHz (VCO = 1, prescaler = 5, output divider =
1), f_out = 400 MHz (driver mode = LVDS)
PARAMETER
MIN
TYP MAX UNIT
phn₁₀₀
phn_1k
phn_10k
phn_100k
phn_1M
phn_10M
phn_20M
J_RMS
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter integrated from 12 kHz to 20 MHz
–99
–107
–115
–119
–128
–144
–145
501
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
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