BQ24157 Datasheet, PDF (6/39 Pages) Texas Instruments – Fully Integrated Switch-Mode Charger With USB Compliance and USB-OTG Support

bq24157
SLUSB80 – SEPTEMBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 2, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), T_J = –40°C to 125°C, T_J = 25°C for typical values
(unless otherwise noted)
PARAMETER
BAD ADAPTOR DETECTION
V_IN(min)
Input voltage lower limit
Deglitch time for VBUS rising above V_IN(min)
Hysteresis for V_IN(min)
I_SHORT
Current source to GND
t_INT
Detection Interval
INPUT BASED DYNAMIC POWER MANAGEMENT
V_{IN_DPM}
Input Voltage DPM threshold programmable
range
VIN DPM threshold accuracy
INPUT CURRENT LIMITING
I_{IN_LIMIT}
Input current limiting threshold
VREF BIAS REGULATOR
V_REF
Internal bias regulator voltage
V_REF output short current limit
BATTERY RECHARGE THRESHOLD
V_(RCH)
Recharge threshold voltage
Deglitch time
STAT OUTPUTS
V_OL(STAT)
Low-level output saturation voltage, STAT pin
High-level leakage current for STAT
I²C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
V_OL
Output low threshold level
V_IL
Input low threshold level
V_IH
Input high threshold level
I_(BIAS)
Input bias current
f_(SCL)
SCL clock frequency
BATTERY DETECTION
I_(DETECT)
Battery detection current before charge done
(sink current) ⁽²⁾
t_DETECT
Battery detection time
SLEEP COMPARATOR
V_(SLP)
Sleep-mode entry threshold,
VBUS – V_CSOUT
V_{(SLP_EXIT)}
Sleep-mode exit hysteresis
Deglitch time for VBUS rising above
V_(SLP) + V_{(SLP_EXIT)}
UNDERVOLTAGE LOCKOUT (UVLO)
UVLO
IC active threshold voltage
UVLO_(HYS)
IC active hysteresis
Power up delay
TEST CONDITIONS
BAD ADAPTOR DETECTION
Rising voltage, 2-mV overdrive, t_RISE = 100 ns
Input voltage rising
During bad adaptor detection
Input power source detection
I_IN = 100 mA
I_IN = 500 mA
T_J = 0°C – 125°C
T_J = –40°C –125°C
T_J = 0°C – 125°C
T_J = –40°C –125°C
VBUS >V_IN(min) or V_(CSOUT) > VBUS(min),
I_(VREF) = 1 mA, C_(VREF) = 1 μF
Below V_(OREG)
V_(CSOUT) decreasing below threshold,
t_FALL = 100 ns, 10-mV overdrive
I_O = 10 mA, sink current
Voltage on STAT pin is 5 V
I_O = 10 mA, sink current
V_(pull-up) = 1.8 V, SDA and SCL
V_(pull-up) = 1.8 V, SDA and SCL
V_(pull-up) = 1.8 V, SDA and SCL
Begins after termination detected,
V_(CSOUT) ≤ V_(BATREG)
2.3 V ≤ V_(CSOUT) ≤ V_(BATREG), V_BUS falling
2.3 V ≤ V_(CSOUT) ≤ V_(BATREG)
Rising voltage, 2-mV overdrive,
t_RISE = 100 ns
V_BUS rising - Exits UVLO
V_BUS falling below UVLO - Enters UVLO
MIN TYP MAX UNIT
3.6
3.8
4.0
V
30
ms
100
200 mV
20
30
40 mA
2
s
4.2
–3%
4.76
V
1%
88
93
98 mA
86
93
98
450
475
500 mA
440
475
500
2
6.5
V
30
mA
100
120
150 mV
130
ms
0.55
V
1 μA
0.4
V
0.4
V
1.2
V
1 μA
3.4 MHz
–0.5
mA
262
ms
0
40
100 mV
140
200
260 mV
30
ms
3.05
3.3 3.55
V
120
150
mV
140
ms
(2) Bottom N-channel FET always turns on for ~30 ns and then turns off if current is too low.
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