BQ24157 Datasheet, PDF (24/39 Pages) Texas Instruments – Fully Integrated Switch-Mode Charger With USB Compliance and USB-OTG Support

bq24157
SLUSB80 – SEPTEMBER 2012
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 31). This releases the bus and stops the communication
link with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to
prevent the slave I²C logic from getting stuck in a bad state. Attempting to read data from register addresses not
listed in this section will result in FFh being read out.
Data Output
by Transmitter
Data Output
by Receiver
Not Acknowledge
Acknowledge
SCL From
Master
START
Condition
1
2
8
Figure 30. Acknowledge on the I²C Bus™
9
Clock Pulse for
Acknowledgement
Recognize START or
REPEATED START
Condition
SDA
MSB
Address
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
Recognize STOP or
REPEATED START
Condition
P
Sr
SCL
S
or
Sr
R/W
ACK
Clock Line Held Low While
Interrupts are Serviced
Figure 31. Bus Protocol
Sr
ACK
or
P
24
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