BQ24157 Datasheet, PDF (26/39 Pages) Texas Instruments – Fully Integrated Switch-Mode Charger With USB Compliance and USB-OTG Support

bq24157
SLUSB80 – SEPTEMBER 2012
www.ti.com
The slave address byte is the first byte received following the START condition from the master device.
Register Address Byte
MSB
LSB
0
0
0
0
0
D2
D1
D0
Following the successful acknowledgment of the slave address, the bus master will send a byte to the IC, which
contains the address of the register to be accessed. The IC contains five 8-bit registers accessible via a
bidirectional I²C-bus interface. Among them, four internal registers have read and write access; and one has only
read access.
REGISTER DESCRIPTION
BIT
B7 (MSB)
B6
B5
B4
B3
B2
B1
B0 (LSB)
Table 3. Status/Control Register (Read/Write)
Memory Location: 00, Reset State: x1xx 0xxx
NAME
TMR_RST/OTG
EN_STAT
STAT2
STAT1
BOOST
FAULT_3
FAULT_2
FAULT_1
READ/WRITE
Read/Write
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
FUNCTION
Write: TMR_RST function, write "1" to reset the safety timer (auto clear)
Read: OTG pin status, 0-OTG pin at Low level, 1-OTG pin at High level
0-Disable STAT pin function, 1-Enable STAT pin function (default 1)
00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault
1-Boost mode, 0-Not in boost mode
Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Bad Adaptor or
V_BUS<V_UVLO,
100-Output OVP, 101-Thermal shutdown, 110-Timer fault, 111-No battery
Boost mode: 000-Normal, 001-VBUS OVP, 010-Over load, 011-Battery voltage is too low,
100-Battery OVP, 101-Thermal shutdown, 110-Timer fault, 111-NA
Table 4. Control Register (Read/Write)
Memory Location: 01, Reset State: 0011 0000
BIT
B7 (MSB)
B6
B5
B4
B3
B2
B1
B0 (LSB)
NAME
Iin_Limit_2
Iin_Limit_1
V_{(LOWV_2)} ⁽¹⁾
V_{(LOWV_1)} ⁽¹⁾
TE
CE
HZ_MODE
OPA_MODE
READ/WRITE
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
00-USB host with 100-mA current limit, 01-USB host with 500-mA current limit, 10-
USB host/charger with 800-mA current limit, 11-No input current limit
Weak battery voltage threshold: 200mV step (default 1)
Weak battery voltage threshold: 100mV step (default 1)
1-Enable charge current termination, 0-Disable charge current termination (default 0)
1-Charger is disabled, 0-Charger enabled (default 0)
1-High impedance mode, 0-Not high impedance mode (default 0)
1-Boost mode, 0-Charger mode (default 0)
(1) The range of the weak battery voltage threshold (V_(LOWV)) is 3.4 V to 3.7 V with an offset of 3.4 V and steps of 100 mV (default 3.7 V,
using bits B4-B5).
BIT
B7 (MSB)
B6
B5
B4
B3
B2
NAME
V_O(REG5)
V_O(REG4)
V_O(REG3)
V_O(REG2)
V_O(REG1)
V_O(REG0)
Table 5. Control/Battery Voltage Register (Read/Write)
Memory Location: 02, Reset State: 0000 1010
READ/WRITE
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
Battery Regulation Voltage: 640 mV step (default 0)
Battery Regulation Voltage: 320 mV step (default 0)
Battery Regulation Voltage: 160 mV step (default 0)
Battery Regulation Voltage: 80 mV step (default 0)
Battery Regulation Voltage: 40 mV step (default 1)
Battery Regulation Voltage: 20 mV step (default 0)
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