BQ24157 Datasheet, PDF (32/39 Pages) Texas Instruments – Fully Integrated Switch-Mode Charger With USB Compliance and USB-OTG Support

bq24157
SLUSB80 – SEPTEMBER 2012
www.ti.com
Select 0402 0.125-W 68-mΩ 2% sense resistor, i.e. Panasonic ERJ2BWGR068.
4. Measured efficiency and total power loss with different inductors are shown in Figure 34. SW node and
inductor current waveform are shown in Figure 35.
Battery Charge Efficiency
90
T_A=25°C,
89
TOKO
VBUS = 5 V,
88
FDK ^{VBAT = 3 V}
87
muRata
86
Inter-Technical
85
84
83
82
500 600 700 800 900 1000 1100 1200 1300
Charge Current - mA
Battery Charge Loss
800
T_A=25°C,
700 VBUS = 5 V,
VBAT = 3 V
600
500
Inter-Technical
400
muRata
TOKO
FDK
300
200
100
500 600 700 800 900 1000 1100 1200 1300
Charge Current - mA
Figure 34. Measured Efficiency and Power Loss
PCB LAYOUT CONSIDERATION
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed
as close as possible to the pin. The output inductor should be placed close to the IC and the output capacitor
connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area
from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation
problems, proper layout to minimize high frequency current path loop is critical. (See Figure 35.) The sense
resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads
connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other
on adjacent layers (do not route the sense leads through a high-current path). (See Figure 36.)
• Place all decoupling capacitors close to their respective IC pins and close to PGND (do not place components
such that routing interrupts power stage currents). All small control signals should be routed away from the
high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per capacitor for small-
signal components). A star ground design approach is typically used to keep circuit block currents isolated
(high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single
ground plane for this design gives good results. With this small layout and a single ground plane, there is no
ground-bounce issue, and having the components segregated minimizes coupling between signals.
• The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
• Place 4.7μF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1μF input capacitor as close to VBUS pin and PGND pin as possible to
make high frequency current loop area as small as possible (see Figure 37).
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