BQ24157 Datasheet, PDF (25/39 Pages) Texas Instruments – Fully Integrated Switch-Mode Charger With USB Compliance and USB-OTG Support

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bq24157
SLUSB80 – SEPTEMBER 2012
H/S Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS-mode. If a transaction is terminated prematurely, the master needs sending a
STOP condition to prevent the slave I2C logic from getting stuck in a bad state.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
I²C Update Sequence
The IC requires a start condition, a valid I²C address, a register address byte, and a data byte for a single
update. After the receipt of each byte, the IC acknowledges by pulling the SDA line low during the high period of
a single clock pulse. A valid I²C address selects the IC. The IC performs an update on the falling edge of the
acknowledge signal that follows the LSB byte.
For the first update, the IC requires a start condition, a valid I²C address, a register address byte, a data byte.
For all consecutive updates, The IC needs a register address byte, and a data byte. Once a stop condition is
received, the IC releases the I²C bus, and awaits a new start conditions.
S SLAVE ADDRESS
R/W
‘0’ (Write)
A REGISTER ADDRESS A DATA
Data Transferred
(n Bytes + Acknowledge)
A/A ^P
From master to IC
From IC to master
A = Acknowledge (SDA LOW)
A = Not acknowledge (SDA
HIGH)
S = START condition
Sr = Repeated START condition
P = STOP condition
(a) F/S-Mode
F/S-Mode
HS-Mode
F/S-Mode
S HS-MASTER CODE
A ^{Sr SLAVE ADDRESS R/W}
‘0’ (write)
A REGISTER ADDRESS A DATA
Data Transferred
(n Bytes + Acknowledge)
A/A ^P
HS-Mode
Continues
(b) HS- Mode
Figure 32. Data Transfer Format in F/S Mode and H/S Mode
Sr Slave A.
Slave Address Byte
MSB
LSB
X
1
1
0
1
0
1
1
Copyright © 2012, Texas Instruments Incorporated
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