BQ24157 Datasheet, PDF (3/39 Pages) Texas Instruments – Fully Integrated Switch-Mode Charger With USB Compliance and USB-OTG Support

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PIN LAYOUT (20-Bump YFF Package)
bq24157
(Top View)
A1
A2
A3
A4
VBUS
VBUS
BOOT
SCL
B1
B2
B3
B4
PMID
PMID
PMID
SDA
C1
C2
C3
C4
SW
SW
SW
STAT
D1
PGND
E1
CSIN
D2
PGND
E2
CD
D3
PGND
D4
OTG
E3
VREF
E4
CSOUT
bq24157
SLUSB80 – SEPTEMBER 2012
NAME
CSOUT
VBUS
PMID
SW
BOOT
PGND
CSIN
SCL
SDA
STAT
PIN
NO.
E4
A1, A2
B1, B2, B3
C1, C2, C3
A3
D1, D2, D3
E1
A4
B4
C4
VREF
E3
CD
E2
OTG
D4
PIN FUNCTIONS
I/O
DESCRIPTION
I
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 μF) to PGND if there are
long inductive leads to battery.
I/O
Charger input voltage. Bypass it with a 1-μF ceramic capacitor from VBUS to PGND. It also provides power to the
load during boost mode .
I/O
Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of 3.3-μF
capacitor from PMID to PGND.
O Internal switch to output inductor connection.
I/O
Bootstrap capacitor connection for the high-side FET gate driver. Connect a 10-nF ceramic capacitor (voltage rating ≥
10 V) from BOOT pin to SW pin.
Power ground
I
Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-μF ceramic capacitor
to PGND is required.
I
I²C interface clock. Connect a 10-kΩ pullup resistor to 1.8V rail (V_AUX= V_{CC_HOST})
I/O I²C interface data. Connect a 10-kΩ pullup resistor to 1.8V rail (V_AUX= V_{CC_HOST})
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128-μs pulse is
O sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive a LED or
communicate with a host processor.
O
Internal bias regulator voltage. Connect a 1µF ceramic capacitor from this output to PGND. External load on VREF is
not recommended.
I
Charge disable control pin. CD=0, charge is enabled. CD=1, charge is disabled and VBUS pin is high impedance to
GND.
Boost mode enable control or input current limiting selection pin. When OTG is in active status, the device is forced to
I
operate in boost mode. It has higher priority over I²C control and can be disabled using the control register. At POR
while in default mode, the OTG pin is used as the input current limiting selection pin. The I²C register is ignored at
startup. When OTG=High, I_{IN_LIMIT} = 500mA and when OTG = Low, I_{IN_LIMIT} = 100mA.
PART NUMBER
bq24157YFFR
bq24157YFFT
ORDERING INFORMATION⁽¹⁾
MARKING
MEDIUM
bq24157A
Tape and Reel
bq24157A
Tape and Reel
QUANTITY
3000
250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2012, Texas Instruments Incorporated
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