TMS320DM6467 Datasheet, PDF (52/334 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403 – DECEMBER 2007
www.ti.com
Table 2-17. Transport Stream Interface 0 (TSIF0) Terminal Functions (continued)
SIGNAL
NAME
VP_CLKO3/
TS0_CLKO
UDTR0/
TS0_ENAO/GP[36]
UDSR0/
TS0_PSTO/
GP[37]
UDCD0/
TS0_WAITIN/
GP[38]
VP_DIN7/
TS0_DOUT7/
TS1_DIN
VP_DIN6/
TS0_DOUT6/
TS1_PSTIN
VP_DIN5/
TS0_DOUT5/
TS1_EN_WAITO
VP_DIN4/
TS0_DOUT4/
TS1_WAITO
VP_DIN3/
TS0_DOUT3
VP_DIN2/
TS0_DOUT2
VP_DIN1/
TS0_DOUT1
VP_DIN0/
TS0_DOUT0
VP_CLKO3/
TS0_CLKO
UDTR0/
TS0_ENAO/GP[36]
UDSR0/
TS0_PSTO/GP[37]
UDCD0/
TS0_WAITIN/GP[38]
UTXD1/URCTX1/
TS0_DOUT7/GP[24]
NO.
AC10
Y12
AB11
AA11
TYPE⁽¹⁾ OTHER⁽²⁾⁽³⁾
DESCRIPTION
TSIF0 PARALLEL OUTPUT (PINMUX0.PTSIMUX = 10)
O/Z
-
DV_DD33
This pin is multiplexed between the VPIF and TSIF0.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
transmit clock output, TS0_CLKO (O/Z).
I/O/Z
IPU
DV_DD33
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
data enable indicator, TS0_ENAO (O/Z) in either synchronous/asynchronous
modes.
I/O/Z
IPU
DV_DD33
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
packet start output indicator, TS0_PSTO (O/Z) in either
synchronous/asynchronous modes.
I/O/Z
IPU
DV_DD33
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), in asynchronous
mode, this pin is the wait input, TS0_WAITIN (I).
This TSIF pin function is not used in synchronous mode.
Y14
AA14
AB14
I/O/Z
IPD
DV_DD33
These pins are multiplexed between the VPIF, TSIF0, and TSIF1.
When parallel TSIF0 output is enabled (PINMUX0.PTSOMUX = 10), and
TSIF1 VPIF_DIN muxing is not enabled (TSSI_MUX ≠ 11), these pins are
the output data bits TS0_DOUT[7:4] (O/Z) in either
synchronous/asynchronous modes.
AC14
Y15
AA15
AB15
AC15
AC10
Y12
AB11
AA11
AB19
I/O/Z
IPD
DV_DD33
These pins are multiplexed between the VPIF and TSIF0.
When parallel TSIF0 output is enabled (PINMUX0.PTSOMUX = 10), these
pins are the output data bits TS0_DOUT[3:0] (O/Z) in either
synchronous/asynchronous modes.
TSIF0 SERIAL OUTPUT (PINMUX0.PTSIMUX = 11)
O/Z
-
DV_DD33
This pin is multiplexed between the VPIF and TSIF0.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
transmit clock output, TS0_CLKO (O/Z).
I/O/Z
IPU
DV_DD33
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
data enable indicator, TS0_ENAO (O/Z) in either synchronous/asynchronous
modes.
I/O/Z
IPU
DV_DD33
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
packet start output indicator, TS0_PSTO (O/Z) in either
synchronous/asynchronous modes.
I/O/Z
IPU
DV_DD33
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), in asynchronous
mode, this pin is the wait input, TS0_WAITIN (I).
This TSIF pin function is not used in synchronous mode.
I/O/Z
IPD
DV_DD33
This pin is multiplexed between UART1, TSIF0, and GPIO.
When serial TSIF0 output is enabled (PINMUX0.PTSOMUX = 11), in
synchronous/asynchronous modes, this pin is the serial output data bit,
TS0_DOUT[7] (O/Z).
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