TMS320DM6467 Datasheet, PDF (283/334 Pages) Texas Instruments – Digital Media System-on-Chip

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6.20.3 VLYNQ Electrical Data/Timing
TMS320DM6467
Digital Media System-on-Chip
SPRS403 – DECEMBER 2007
Table 6-85. Timing Requirements for VLYNQ_CLOCK Input (see Figure 6-71)
NO.
1
t_c(VCLK)
2
t_w(VCLKH)
3
t_w(VCLKL)
4
t_t(VCLK)
Cycle time, VLYNQ_CLOCK
Pulse duration, VLYNQ_CLOCK high
Pulse duration, VLYNQ_CLK low
Transition time, VLYNQ_CLOCK
-594
MIN
10
3
3
MAX
3
UNIT
ns
ns
ns
ns
Table 6-86. Switching Characteristics Over Recommended Operating Conditions for VLYNQ_CLOCK
Output (see Figure 6-71)
NO.
PARAMETER
1 t_c(VCLK)
Cycle time, VLYNQ_CLOCK
2 t_w(VCLKH) Pulse duration, VLYNQ_CLOCK high
3 t_w(VCLKL) Pulse duration, VLYNQ_CLOCK low
4 t_t(VCLK)
Transition time, VLYNQ_CLOCK
-594
MIN MAX
10
4
4
3
UNIT
ns
ns
ns
ns
VLYNQ_CLOCK
1
4
2
4
3
Figure 6-71. VLYNQ_CLOCK Timing for VLYNQ
Table 6-87. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the
VLYNQ Module (see Figure 6-72)
NO PARAM
. ETER
1 ^td(VCLKH- Delay time, VLYNQ_CLOCK high to VLYNQ_TXD[3:0] invalid
TXDI)
2 ^td(VCLKH- Delay time, VLYNQ_CLOCK high to VLYNQ_TXD[3:0] valid
TXDV)
-594
FAST MODE
SLOW MODE
MIN MAX
MIN MAX
1
2.25
UNIT
ns
7
8.5 ns
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