TMS320DM6467 Datasheet, PDF (300/334 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403 – DECEMBER 2007
Table 6-102. General Input Timing Requirements in Slave Mode⁽¹⁾
NO.
MIN
9
t_c(CLK)
Cycle time, SPI_CLK
2P
10
t_w(CLKH)
Pulse width, SPI_CLK high
P
11
t_w(CLKL)
Pulse width, SPI_CLK low
P
Setup time, SPI_SIMO data valid before receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
2P
polarity = 0, phase = 0
Setup time, SPI_SIMO data valid before receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
2P
15
t_su(SIMO-CLK)
polarity = 0, phase = 1
Setup time, SPI_SIMO data valid before receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
2P
polarity = 1, phase = 0
Setup time, SPI_SIMO data valid before receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
2P
polarity = 1, phase = 1
Hold time, SPI_SIMO data valid after receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
2
polarity = 0, phase = 0
Hold time, SPI_SIMO data valid after receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
2
16
t_h(CLK-SIMO)
polarity = 0, phase = 1
Hold time, SPI_SIMO data valid after receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
2
polarity = 1, phase = 0
Hold time, SPI_SIMO data valid after receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
2
polarity = 1, phase = 1
(1) P = period of SPI core clock
Master Mode — Additional
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MAX
UNIT
ns
ns
ns
ns
ns
Table 6-103. Additional Output Switching Characteristics of 4-Pin Enable Option in Master Mode⁽¹⁾⁽²⁾
NO.
17
t_d(EN-CLK)
PARAMETER
Delay time, slave assertion of SPI_EN active to first SPI_CLK
rising edge from master, 4-pin mode, polarity = 0, phase = 0
Delay time, slave assertion of SPI_EN active to first SPI_CLK
rising edge from master, 4-pin mode, polarity = 0, phase = 1
Delay time, slave assertion of SPI_EN active to first SPI_CLK
falling edge from master, 4-pin mode, polarity = 1, phase = 0
Delay time, slave assertion of SPI_EN active to first SPI_CLK
falling edge from master, 4-pin mode, polarity = 1, phase = 1
MIN
MAX UNIT
3P + 6
0.5T + 3P + 6
ns
3P + 6
0.5T + 3P + 6
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 6-77 shows only polarity = 0, phase = 0 as an example. In this case, the Master SPI is ready with new data before SPI_EN
assertion.
300 Peripheral Information and Electrical Specifications
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